Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-10
2002-11-05
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S769000, C438S775000, C438S275000, C438S770000
Reexamination Certificate
active
06475862
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device with MIS (Metal-Insulator-Semiconductor) field effect transistors and process for fabricating the semiconductor integrated circuit device.
DESCRIPTION OF THE RELATED ART
Plural circuit elements are integrated on a semiconductor substrate, and are selectively connected for forming an integrated circuit. The integrated circuit is broken down into a signal interface and a functional circuit. Signals are transferred between the functional circuit and the outside thereof through the signal interface. The functional circuit processes signals carried with pieces of data information, and temporarily stores the result of the data processing.
The data processing is assigned to an arithmetic and logic circuit, and a memory circuit stores the results. Typical examples of the memory circuit are a dynamic random access memory and a static random access memory, and the arithmetic and logic circuit is, by way of example, implemented by CMOS (Complementary Metal Oxide Semiconductor) logic gates. MOS (Metal Oxide Semiconductor) field effect transistors are, by way of example, used for the signal interface. Thus, field effect transistors are major circuit components of the integrated circuit.
One of the goals in the technical field is to operate the field effect transistors at high speed under low power voltage. A field effect transistor with a thin gate insulating layer is suitable for the technical goal. The miniaturization, high-speed and low power consumption are still required for the semiconductor integrated circuit device. The functional circuit are formed by using the component field effect transistors, the gate insulating layers of which get thinner and thinner for operating under the low power voltage. However, the solution is less employable in the signal interface. The external signals are applied to the signal interface, and the voltage range of the external signals is independent of the internal power supply system in the integrated circuit. Thus, the external signal is a dominating factor in the signal interface. In this situation, the component field effect transistors of the signal interface are designed separately from those of the functional circuit, and the gate insulating layers thereof are usually thicker than those of the component field effect transistors of the functional circuit. In a semiconductor integrated circuit device commercially obtainable, the component field effect transistors of the signal interface are designed to have the gate insulating layers of
7
nanometers thick, and the component field effect transistors of the functional circuit are designed to have the gate insulating layers of 4 nanometers thick.
The design and research efforts are been made for the field effect transistors with the emphasis put on faster transistors. The speed-up is not constantly required over the integrated circuit. The speed-up is more important to the arithmetic and logic circuit than another part of the integrated circuit. The gate insulating layer is going to reduce from 7 nanometers thick to 5 nanometers thick for the circuit components of the signal interface and from 4 nanometers thick to 2 nanometers thick for the functional circuit.
The thin gate insulating layers surely accelerate the switching actions of the component field effect transistors. However, a problem is encountered in the component field effect transistors in the leakage current flowing through the thin gate insulating layers.
FIG. 1
illustrates the leakage current density in terms of the thickness Tox of the gate insulating layer formed of silicon oxide. The axis of abscissas is indicative of the thickness of the gate insulating layer formed of silicon oxide. On the other hand, the axis of coordinates is indicative of the leakage current density. When the gate insulating layer is biased with 1.5 volts, the leakage current density is varied in inversely exponentially proportional to the thickness of the gate insulating layer. Thus, the thin gate insulating layers give rise to increase of the leakage current flowing therethrough.
The leakage current is undesirable for the integrated circuit. First, the power consumption is increased in the idling state. Second, the thin gate insulating layers are damaged or deteriorated due to the leakage current. Third, a piece of data information is destroyed when the field effect transistors form a memory cell. This means that the leakage current sets a limit to the thickness of the gate insulating layer. The limit is varied depending upon the operating environment of the field effect transistor such as, for example, the bias voltage and function of the associated circuitry.
As will be understood, an integrated circuit includes field effect transistors different in thickness, and the difference in thickness is dependent on the requirements for a circuitry. Although the manufacturer makes the gate insulating layers different in thickness between the component field effect transistors of the signal interface and the field effect transistors of the functional circuit both integrated on a semiconductor substrate, the difference in thickness is of the order of 3 nanometers thick. It is said that the limit to the gate insulating layers is 3 nanometers to 1 nanometer. Even if the manufacturer designs field effect transistors of an integrated circuit to have the gate insulating layers different in thickness of the order of 0.5 nanometer, the integrated circuit is not feasible. For example, a manufacturer is assumed to design field effect transistors with the gate insulating layers of 2.0 nanometers thick for the arithmetic and logic circuit and field effect transistors with the gate insulating layers of 2.5 nanometers thick for the memory circuit. The manufacturer fabricates the two kinds of field effect transistors different in thickness on a semiconductor substrate through the prior art process. However, the gate insulating layers are not properly fallen within the range around 2.0 nanometers thick and the range around 2.5 nanometers thick upon completion of the fabrication process. The gate insulating layers are randomly fallen within the range around 2.0 nanometers thick and the range around 2.5 nanometers thick, and it is impossible to discriminate the design intention from the field effect transistors fabricated on the semiconductor substrate. Thus, the difference of 1 nanometer thick is the limit to the gate insulating layers of the order of 4 nanometers thick or less in so far as the field effect transistors are fabricated through known process sequences.
Description is hereinbelow made on the prior art process sequences. The first prior art process is used for a semiconductor integrated circuit device having three regions assigned to different circuits. The first region is referred to as a core region, and a CMOS logic circuit is assigned to the core region. The second region is referred to as an SRAM (Static Random Access Memory) region, and the SRAM region is assigned to a static random access memory. The component field effect transistors of the CMOS logic circuit are different in thickness of the gate insulating layers from the component field effect transistors of the static random access memory. The third region is referred to as a peripheral region, and an input-and- output circuit is assigned to the peripheral region. The component field effect transistors of the input-and-output circuit are different in thickness of the gate insulating layers from those of the CMOS logic circuit and those of the static random access memory.
FIGS. 2A
to
2
J,
3
A to
3
J and
4
A to
4
J illustrate the first prior art process for fabricating the semiconductor integrated circuit device.
FIGS. 2A
to
2
J show a cross section of the core region, and a gate insulating layer is adapted to 1.8 nanometers thick.
FIGS. 3A
to
3
J show a cross section of the SRAM region, and a gate insulating layer is adapted to 4.0 nano
Chaudhuri Olik
Duy Mai Anh
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