Method of forming a system on chip (SOC) with nitride read...

Details Method of forming a system on chip (SOC) with nitride read... Method of forming a system on chip (SOC) with nitride read...

2001-08-07

2002-08-13

Christianson, Keith (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S954000, C438S128000

Reexamination Certificate

active

06432778

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention provides a method of forming a system on chip(SOC), and more particularly, to a method of forming a system on chip embedded with nitride read only memory(NROM) and mask read only memory by utilizing nitride read only memory.
2. Description of the Prior Art
A Read only memory(ROM) device is a semiconductor device for data storage. It is composed of a plurality of memory cells and is widely applied in the data storage and memory system of computer nowadays. The read only memory can be classified into mask ROM, programmable ROM(PROM), erasable programmable ROM(EPROM), electrically erasable programmable ROM(EEPROM), nitride read only memory(NROM) and flash ROM according to the method for data storage. The main feature of read only memory is that once data or information is stored, it will not disappear because of an interruption or power cut, and so therefore the read only memory is also called non-volatile memory.
The character of nitride read only memory(NROM) is to utilize silicon nitride isolation dielectric layer as a charge trapping medium. Since the silicon nitride layer is extremely dense, hot electrons can tunnel into the silicon nitride layer and become trapped inside it through MOS transistor. This further forms an inhomogeneous density distribution in order to accelerate the rate of data reading and avoid leakage current. While the flash ROM utilizes a floating gate composed of polysilicon or metal to store charges, therefore it has an extra gate except the control gate. The former one has the advantage of a simple manufacturing process and low cost. Since the latter one needs to be made with a floating gate-inter-dielectric layer-control gate structure, and the quality of the material in the three-layer structure is very important, it is necessary to coordinate with an appropriate process and results in a more complex manufacturing process and higher cost.
In the modern electronics industry, it is often felt that the read only memory and the non-volatile memory need to exist in various products at the same time. In contrast to two devices manufactured in a single chip, the two devices manufactured in two separate chips will occupy more room and also raise the cost. Therefore in U.S. Pat. No. #5,403,764, Yamamoto et al. had proposed a method of implanting ROM code into the flash ROM device in the ROM region by utilizing an ion implantation process during flash ROM manufacturing process, or in other words, completing the “read” procedure, then completing the manufacturing process of the flash ROM. So the read only memory is established in some portion of the flash ROM chip.
Please refer to
FIG. 1
to FIG.
5
.
FIG. 1
to
FIG. 5
are schematic diagrams of a process for making the flash ROM chip
10
comprising read only memory
24
according to the prior art. As shown in
FIG. 1
, the prior art method of forming a flash ROM chip
10
comprising read only memory
24
is to first provide a semiconductor wafer
11
comprising P type silicon base
12
, then utilize a thermal oxidation process with a temperature about 1100° C. and process time about 90 minutes to form a silicon dioxide (SiO
2
) layer
14
with a thickness several thousands angstroms(Å) on the surface of the silicon base
12
not covered by the oxidation-protective film(not shown), such as silicon nitride(Si
3
N
4
). After that the remaining silicon nitride layer (not shown) is removed and a very thin silicon oxide layer
16
is preserved between the silicon dioxide layer
14
and the silicon dioxide layer
14
, that is, in between each field oxide layer. In other words,utilizing local oxidation(LOCOS) to form the isolation between each transistor completed afterwards.
As shown in
FIG. 2
, an ion implantation process in the read only memory area
18
on the flash ROM chip
10
is performed. The ion implantation process utilizes an accelerating energy ranging from 40 to 50 keV, Boron ion dosage ranging from 1E12 to 3E12/cm
2
to form a first P+ type doping area
22
with ion concentration ranging from 10
16
to 10
17
/cm
3
. The objective of the ion implantation process is to adjust the threshold voltage(Vth) of the first read only memory(not shown) in the read only memory area
18
to a first specific value, so the threshold voltage of the first read only memory(not shown) is adjusted to around 1V and store a data “1”.
As shown in
FIG. 3
, a first photolithography process is performed in order to form a first mask
31
out of the read only memory area
18
and the read only memory
26
with a second specific value as its threshold voltage. Thereafter an ion implantation process is performed on the flash ROM chip
10
, the ion implantation process utilizing the accelerating energy ranged from 40 to 50 keV, Boron ion dosage ranging from 5E12 to 1E13/cm
2
to form a second P+ type dopant area
32
with final ion concentration ranged from 10
17
to 10
18
/cm
3
. The objective of the ion implantation process is to adjust the threshold voltage(Vth) of the second read only memory(not shown) in the read only memory area
18
to a second specific value, so the threshold voltage of the second read only memory(not shown) is adjusted to around 7V and store a data “0”.
As shown in
FIG. 4
, a first polysilicon layer
34
, an interlayer isolation layer
36
composed of silicon nitride or silicon oxide and a second polysilicon layer
38
on the flash ROM chip
10
are then deposited. After that a second photolithography process is performed in order to form a double gate
39
of the first read only memory
24
, the second read only memory
26
and the flash ROM
40
. Although the gate structure of the first, the second read only memory
24
,
26
is single layered in general and the double gate
39
with three layered structure is not required, all of the gates are completed with the same process steps in the prior art method in order to reduce the number of process steps.
As shown in
FIG. 5
, a phosphorous ion implantation process is performed by utilizing a third mask(not shown) in order to form a N+ source
41
, a N+ drain
42
at either side of the double gate
39
of the first, the second read only memory
24
,
26
to complete the manufacturing of the first, the second read only memory
24
,
26
. Finally another phosphorous ion implantation process is performed by utilizing a fourth mask(not shown) in order to form a N+ source
43
, a N+ drain
44
at either side of the double gate
39
of the flash ROM
40
to complete the manufacturing of the flash ROM
40
. Therefore not only the read only memory
24
,
26
on the flash ROM chip
10
are written with “0” or “1” but also the flash ROM
40
is completed by just adding two process steps for threshold voltage adjustment in the standard flash ROM manufacturing process.
However the flash ROM chip in the prior art only comprises some read only memory, the objective of system on chip is not achieved. Moreover the cost of flash ROM is more expensive, not suitable to the manufacturing of system on chip. Therefore it is very important to develop a system on chip to utilize the device with cheaper cost and its manufacturing process to simultaneously make the read only memory and the nitride read only memory on the same chip, and omit the electrical writing step for the general non-volatile memory after completion.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a system on chip(SOC), and more particularly, to a method of forming a system on chip embedded with nitride read only memory and read only memory by utilizing nitride read only memory.
In the first preferred embodiment of the present invention, the system on chip is made on the surface of the semiconductor wafer and utilizes the manufacturing process of the nitride read only memory(NROM) to simultaneously make the read only memory and the nitride read only memory. The method according to the present invention comprises forming an ONO dielec

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