Semiconductor processing methods

Details Semiconductor processing methods Semiconductor processing methods

2000-10-05

2002-10-15

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000

Reexamination Certificate

active

06465314

ABSTRACT:

TECHNICAL FIELD
The invention pertains to semiconductor processing methods of implanting dopants into semiconductor substrates. The invention has particular application to methods of forming shallow implant regions.
BACKGROUND OF THE INVENTION
A prior art semiconductive device
12
is shown as part of a semiconductor wafer fragment
10
in FIG.
1
. Device
12
is a field effect transistor formed proximate a semiconductive substrate
14
. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Field effect transistor
12
comprises a gate stack
16
comprising a gate oxide layer
18
, a polysilicon layer
20
, a silicide layer
22
and an insulative capping layer
24
. Insulative capping layer
24
can comprise, for example, silicon nitride or silicon oxide. Silicide layer
22
can comprise, for example, tungsten silicide. Polysilicon layer
20
typically comprises conductively doped polysilicon, and gate oxide layer
18
comprises an insulative material, such as silicon oxide.
Spacers
26
are formed adjacent gate stack
16
. Spacers
26
typically comprise an insulative material, such as silicon nitride or silicon dioxide.
Source/drain regions
28
are formed within substrate
14
, and laterally offset from gate stack
16
by about a thickness of spacers
26
. The formation of source/drain regions
28
typically comprises implanting a conductivity-enhancing dopant into substrate
14
. Such implanting occurs after formation of spacers
26
to accomplish the shown lateral displacement of source/drain regions
28
from gate stack
16
.
The dopant type within source/drain regions
28
and substrate
14
will vary depending on whether field effect transistor
12
is an n-type metal-oxide semiconductor (NMOS) or a p-type metal-oxide semiconductor (PMOS) transistor. For an NMOS transistor, source/drain regions
28
will predominately comprise n-type conductivity enhancing dopant, and substrate
14
will have a light background p-type dopant concentration. In contrast, if field effect transistor
12
is a PMOS transistor, source/drain regions
28
will predominately comprise p-type conductivity-enhancing dopant, and substrate
14
will have a light background n-type dopant concentration.
Lightly doped diffusion regions (LDD regions)
29
are formed beneath spacers
26
and constitute a part of the diffusion region. LDD regions
29
comprising a same dopant type as source/drain regions
28
. LDD regions
29
are typically formed by implanting a dopant into substrate
14
after forming gate stack
16
and before forming spacers
26
. Halo regions (not shown) can also be formed as part of the diffusion region. The halo regions will comprise an opposite type dopant as source/drain regions
28
, and will typically be formed at junctions between regions
28
and
29
, and substrate
14
.
A continuing goal in semiconductor device fabrication is to minimize the device size. As field effect transistors become increasingly smaller, they become increasingly susceptible to short-channel effects. One way of reducing short-channel effects is to reduce a vertical depth of source/drain regions
28
. In other words, to form shallow source/drain regions (i.e., source/drain regions that have a lowermost junction boundary that is less than 0.2 microns deep).
Forming shallow implants can be difficult. Generally, shallow implants cannot be formed simply by lowering implant energy, because such lower implant energy results in decreased focus of the implant, and corresponding loss of implant control. Accordingly, complex methods have been developed for forming shallow implants. In one method, a dopant is implanted into a first layer, such as a silicide, and then out-diffused from the first layer into a substrate to form a shallow implant. In another method a conductivity-enhancing dopant is implanted through an inorganic layer, such as silicon dioxide, and into an underlying substrate to form a shallow implant within the substrate. The inorganic layer must generally be removed from over the substrate after the implanting to enable further processing. Removal of the inorganic layers from semiconductive substrates is difficult.
For the above-discussed reasons, it is desirable to develop alternative methods for forming shallow implant regions in semiconductive substrates.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a semiconductor processing method in which an organic layer is formed over a semiconductive substrate, and a conductivity-enhancing dopant is implanted through the organic layer and into the semiconductive substrate.
In another aspect of the invention, a semiconductive substrate is provided and source and drain locations are defined within the semiconductive substrate. An organic layer is formed over the source and drain locations. A conductivity-enhancing dopant is implanted through the organic layer and into the source and drain locations to form source and drain implant regions within the source and drain locations. A transistor gate is formed proximate the source and drain implant regions.
In yet another aspect of the invention, a transistor gate is formed over a semiconductive substrate and source/drain locations are defined within the semiconductive substrate proximate the transistor gate. A polyimide layer is formed over the transistor gate and over the source/drain locations. Photoresist is deposited over the polyimide layer. The photoresist is patterned to form openings over the source/drain locations. A conductivity-enhancing dopant is implanted into the openings, through the polyimide layer and into the source/drain locations.


REFERENCES:
patent: 4978594 (1990-12-01), Bruce et al.
patent: 5069747 (1991-12-01), Cathey et al.
patent: 5395781 (1995-03-01), Wilhoit
patent: 5489540 (1996-02-01), Liu et al.
patent: 5776811 (1998-07-01), Wang et al.
patent: 6165856 (2000-12-01), Jiang et al.
patent: 6248629 (2001-06-01), Liu et al.
Silicon Processing for the VLSI Era—vol. 1—Process Technology; S. Wolf and R.N. Tauber; pp. 321-327, 428-429, 1986.
Silicon Processing for the VLSI Era—vol. 2—Process Integration; S. Wolf; pp. 154-160, 1990.
Silicon Processing for the VLSI Era—vol. 3—The Submicron MOSFET; S. Wolf; pp. 307-308, 1993.
Joint University and Industry Investigation of Polymide for Thin Film Organic Dielectrics for VLSI Interlevel Applications; K.H. Hesler, L.F. Fuller, C. Yue, D. Taylor and S. Popli1989 IEEE Eighth Biennial University/Government Industry Symposium; pp. 95-101.
Evaluation of 0.18 micron Ultra-Shallow Doping Technologies: a SEMATECH/uNIVERSITY/iNDUSTRY Cooperative Research Effort; Eleventh Biennial University/Government/Industry Microelectronics Symposium; Emi Ishida and Larry Larson; pp. 105-107.
Integration of Vapor Deposited Polyimide into a Multichip Module Packaging Process; Vladimir Liberman, Vincent Malba, and Anthony F. Bernhardt; IEEE Transactions on Components, Paging and manufacturing technology, Part B; Feb. 1997; pp. 13-16.
Analytical Circuit Model Approach to Charging Damage in Plasma/Implantation Processing; William G. En, Ben P. Shieh, and Nathan W. Cheung; 1996 1stInternational Symposium on Plasma Process-Induced Damage; May 13-14, 1996.

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