Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-25
2002-12-10
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S433000
Reexamination Certificate
active
06492220
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device such as a metal oxide semiconductor (MOS) transistor partitioned by a shallow trench isolation (STI) layer.
2. Description of the Related Art
When manufacturing a MOS transistor, impurities are introduced into a semiconductor substrate under a gate electrode, thus adjusting the threshold voltage of the MOS transistor. On the other hand, in a prior art manufacturing method, in order to partition MOS transistors from each other, an STI layer made of silicon oxide has been introduced. This will be explained later in detail.
In the above-described prior art method, however, when the channel width as well as the channel length has been reduced, a so-called narrow channel width effect becomes notable. For example, in an N-channel MOS transistor, boron atoms are introduced into a silicon substrate under a gate electrode to adjust the threshold voltage. In this case, boron atoms are segregated by the STI layer, so that the concentration of boron atoms is made lower at the ends of a channel in the width direction than at the center thereof. This decreases the threshold voltage of the N-channel MOS transistor.
Note that, in a P-channel MOS transistor, the same narrow channel width effect occurs. That is, arsenic or phosphorus ions are implanted to decrease the threshold voltage. In this case, arsenic or phosphorus atoms are also segregated by the STI layer, so that the concentration of arsenic or phosphorus atoms is made higher at the ends of a channel in the width direction than at the center thereof. This also decreases the threshold voltage of the P-channel MOS transistor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of suppressing the narrow channel width effect caused by an STI layer.
According to the present invention, in a method for manufacturing a semiconductor device, a shallow trench isolation layer made of silicon oxide is formed in a semiconductor substrate to partition an area for forming a MOS transistor. Then, first impurities are introduced into the MOS transistor forming area to adjust a threshold voltage of the MOS transistor. Then, second impurities are introduced into end portions of the MOS transistor forming area of the semiconductor substrate.
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Blum David S
Choate Hall & Stewart
NEC Corporation
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