Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-08-15
2002-10-29
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S201000, C365S230060
Reexamination Certificate
active
06473347
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
The present application is based on Japanese Priority Patent Application No. 2000-264357 filed on Aug. 31, 2001, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to word line precharge in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
Semiconductor memory devices such as DRAMs are shipped after various tests thereof are completed. A stress test is performed in order to detect initial faults of semiconductor memory devices. The stress test is also called an acceleration test, and tests semiconductor memory devices in such a manner that parameters such as the electric field and temperature are set equal to values higher than those used in the actual environment.
For example, the stress test of semiconductor memory devices applies a voltage higher than that used normally to memory cells in order to inspect initial faults. In the stress test, it will take a very long time to select and precharge (reset) word lines one by one as in the case of the normal operation. Taking into account the above, a word line multi-selection test has been proposed.
In the word line multi-selection test, a plurality of word lines are sequentially selected at one time. Then, a single precharge command is externally applied to the semiconductor memory device. This makes it possible to precharge the selected word lines at one time.
However, a large number of word lines is precharged at one time only by applying the single precharge command to the device. This needs a large amount of peak current in precharging, and the ground potential VSS may float toward a positive power supply voltage VDD. Such floating of the ground potential VSS makes a “fault” decision on the device. In this case, it cannot be determined whether the fault results from an original or initial fault or one-time precharging of word lines.
SUMMARY OF THE INVENTION
A general object of the present invention is to provide a semiconductor device having a memory in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor device having a memory in which the ground potential can be stably held even when a plurality of word lines are driven at one time.
The above objects of the present invention are achieved by a semiconductor device comprising: a plurality of word lines selectable in a predetermined mode; and a circuit that precharges the plurality of word lines selected in the predetermined mode in a time division manner. The above objects of the present invention are also achieved by a semiconductor device comprising: memory cell arrays; and a precharge controller precharging word lines of the memory cell arrays on an array basis in a time division manner.
REFERENCES:
patent: 4914632 (1990-04-01), Fujishima et al.
patent: 5381373 (1995-01-01), Ohsawa
patent: 5615164 (1997-03-01), Kirihata et al.
patent: 5619460 (1997-04-01), Kirihata et al.
Fujioka Shin-ya
Funya Akihiro
Mori Katsuhiro
Arent Fox Kintner Plotkin & Kahn
Fujitsu Limited
Mai Son
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