Method to fabricate dual-metal CMOS transistors for sub-0.1...

Details Method to fabricate dual-metal CMOS transistors for sub-0.1... Method to fabricate dual-metal CMOS transistors for sub-0.1...

2001-03-02

2002-06-25

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S183000

Reexamination Certificate

active

06410376

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating dual-metal transistors in the fabrication of integrated circuits.
(2) Description of the Prior Art
For sub-0.1 &mgr;m CMOS technology, there are a number of issues. The choice of gate dielectric is one issued that will not be addressed here. Other issues related to the gate stack include:
1) Metal gates are needed to replace conventional polysilicon gates in order to reduce poly depletion effects. Depletion effects translate to a reduction in the electric field across the gate dielectric (Eox) and hence inversion charge density; that is, lower drive current. The effect will become more pronounced with smaller gate geometries due to smaller-energy gate implants which are coupled with ultra-shallow junction formation.
2) Metal gates are needed to replace conventional salicided polysilicon gates. Low gate resistance is difficult to achieve with conventional salicide technology due to the conflicting demands of good junction integrity and low gate resistance. On the source/drain, a silicide thickness of less than 20 nanometers is required when gate geometries reach below 70 nm for low specific contact resistivity. On the other hand, it is expected that the silicide thickness on the gate must be at least 45 nm in order to attain a sheet resistance of less than 5 ohms/sq for low signal propagation delay.
3) Different metals are needed for n+ and p+ gates due to gate work function considerations in order to achieve symmetrically low threshold voltages (for low-power devices such as portables) for the NFETs and PFETs in bulk CMOS.
It is desired to provide a process to address these various concerns.
U.S. Pat. No. 6,027,961 to Maiti et al shows a process for forming PMOS and NMOS gates having different work functions. U.S. Pat. No. 6,001,698 to Kuroda discloses a process for forming CMOS gates using an inverse gate process. U.S. Pat. No. 5,786,256 to Gardner et al shows an inverse polysilicon gate process.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the invention is to provide a process for forming metal gates for CMOS transistors in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming dual-metal gate CMOS transistors in the fabrication of integrated circuits.
Another object of the invention is to provide a process for forming dual-metal gate CMOS transistors for sub-0.1 &mgr;m ULSI integration.
Yet another object of the invention is to provide a process for forming dual-metal gate CMOS transistors with shallow junctions for sub-0.1 &mgr;m ULSI integration.
In accordance with the objects of the invention, a method for forming a dual-metal gate CMOS transistors is achieved. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A gate dielectric layer is formed overlying the semiconductor substrate in each of the active areas. A nitride layer is deposited overlying the gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates. Thereafter, the source/drain regions are silicided. A dielectric layer is deposited overlying the second dummy gates and silicided source/drain regions and planarized to the second dummy gates. Thereafter, the second dummy gates are removed, leaving gate openings in the dielectric layer. A mask is formed over the PMOS active area. A first metal layer is deposited in the gate opening in the NMOS active area and planarized to the mask. The mask is removed. A second metal layer is deposited in the gate opening in the PMOS active area. The first and second metal layers are polished away to the dielectric layer thereby forming a first metal gate within the gate opening in the NMOS active area and forming a second metal gate within the gate opening in the PMOS active area to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.


REFERENCES:
patent: 5731239 (1998-03-01), Wong et al.
patent: 5786256 (1998-07-01), Gardner et al.
patent: 6001698 (1999-12-01), Kuroda
patent: 6027961 (2000-02-01), Maiti et al.
patent: 6107130 (2000-08-01), Fulford, Jr. et al.
patent: 6156593 (2000-12-01), Peng et al.
patent: 6207482 (2001-03-01), Shih et al.
patent: 6214656 (2001-04-01), Liaw
patent: 6265251 (2001-07-01), Jun et al.
Semiconductor International, “Strippers No More: Aqueous Approaches to Residue Removal”, pp. 84-86, Dec. 1999.

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