Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-06
2002-02-19
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S303000, C438S306000
Reexamination Certificate
active
06348384
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a device lightly doped drain (LDD) structure and, more particularly, to a device LDD structure using organic polymer as a covering layer to cover over a photo resist.
BACKGROUND OF THE INVENTION
The fabrication process of today integrated circuits (ICs) is very complicated. In order to meet the requirement of low cost and high integration, device sizes need to shrink continually. For instance, the channel length of a transistor shrinks from 0.35 micrometer in 1996 to 0.18 micrometer in 1999, and this trend will maintain up to 2010 with a channel length smaller than 0.10 micrometer. When the device gets smaller, its channel length shrinks accordingly, and the operating speed of the transistor will get faster. However, the channel length of a MOS transistor cannot shrink unlimitedly. When the channel length shrinks to a certain extent, problems originated from shortening of channel length will arise. This phenomenon is called short channel effect. Moreover, when the channel length shrinks (smaller than 1 micrometer), the threshold voltage of the device is no longer constant, and will decrease along with shortening of the channel length.
In addition to resulting in a reduction of the threshold voltage, short channel effect will also bring about the phenomenon of hot electron effect, thereby affecting the operation of a MOS transistor. Generally speaking, a prior art method of resolving hot electron effect resulted from short channel effect is lightly doped drain, briefly termed LDD. As shown in
FIG. 1
, in this MOS structure, a gate
12
is formed on a silicon wafer
10
. An n-type region used as an LDD
18
, which has a lower doping than an n-type source
14
and an n-type drain
16
, is added at the source
14
and the drain
16
near the channel in the silicon wafer
10
.
Evidently, the channel electric field distribution of a MOS having the LDD
18
will shift toward the drain
16
, and the magnitude of the electric field will be lower than that of a MOS without the LDD. Therefore, influence of hot electron effect will lessen. Moreover, hot electron effect has another influence on a MOS. In addition that most of the electrons generated due to impact of hot electrons are absorbed by the drain
16
, part electrons will pass through a silicon oxide
20
and move toward the gate
12
. Most of these electrons will be trapped in the silicon oxide
20
, hence changing the charge quantity Q
OX
of the silicon oxide
20
. Because Q
OX
increases continually with the operation of the MOS, the threshold voltage will thus be changed. The design of the LDD
18
can also decrease the occurrence of this problem. Therefore, the design of LDD has been widely applied to short channel NMOS and CMOS semiconductor devices. The fabricating method of LDD commonly used in semiconductor devices in the prior art is illustrated below with a MOS device structure as an example. A MOS structure is composed of three different electrodes: a gate, a source, and a drain. The gate of a MOS is first fabricated in the active region of the surface of a silicon wafer. Next, the fabrication of the source and drain of a MOS depends on the gate used as a mask to complete the fabrication of the main body of an NMOS transistor. As shown in FIG.
2
(
a
), a gate
22
of a MOS is used as a mask. Next, phosphorous (P) is used as an ion source to perform ion implantation of P ions to a silicon wafer
24
, hence forming an N-implanted region
26
. The implanted region has a lower concentration of about the order of 10
13
/cm
3
, and is used mainly as an LDD for preventing the occurrence of short channel effect. Next, as shown in FIG.
2
(
b
), a silicon oxide
28
used as a gate spacer is deposited on the surface of the silicon wafer
24
by means of chemical vapor deposition (CVD). Before etching the spacer
30
to the silicon wafer
24
, the silicon wafer
24
with the LDD N-implanted region can be sent into a thermal diffusion furnace beforehand. Diffusion of P atoms is performed at a high temperature of about 900 to 1000° C. Silicon atomic structure on part surface of the silicon wafer
24
damaged due to ion implantation is thus simultaneously annealed. Subsequently, etching of the spacer
30
is performed to the silicon wafer
24
covered by the silicon oxide
28
by means of anisotropic etch. Anisotropy, which is characteristic of dry etch, is utilized to remove most of the silicon oxide
28
deposited on the silicon wafer
28
. Because the silicon oxide
28
situated above the side wall of the gate
22
is thicker than other parts thereof, it will not be completely removed, hence forming the spacer
30
shown in FIG.
2
(
c
). In addition that this spacer can be used to separate the gate
22
and the other two electrodes of MOS, most important, heavy doping of the source and the drain can be performed using the structure formed of this spacer and the gate
22
. This step is called N
+
-implantation, wherein the gate
22
having the spacer
30
is used as a mask, and phosphorous or arsenic is used as an ion source, thereby performing N
+
-implantation of high concentration and deeper depth to the silicon wafer
24
. The N
+
-implanted regions used as a source
32
and a drain
34
have a concentration of about 10
15
/cm
3
, as shown in FIG.
2
(
d
). The part of the N-implanted region where N
+
-implantation is not performed is an LDD
36
. A transistor structure with an LDD is thus completed.
As can be known from the above description, the fabrication of LDD plays a very important role in the electrical characteristics of semiconductor devices. However, the above method does not apply to mask ROMs, resulting in unstable threshold voltages and relative increase of leakage currents thereof. Accordingly, the present invention proposes a new LDD fabricating method, which can extensively apply to LDDs of semiconductor devices such as mask ROMs to prevent semiconductor devices from generating short channel effect.
SUMMARY OF THE INVENTION
The primary object of the present invention is to provide a method of using organic polymer as a covering layer for a device LDD structure, wherein ions of different energies and kinds are implanted into the same region of different line widths to achieve the effect of LDD.
Another object of the present invention is to apply a covering layer of organic polymer on a photo resist to change the magnitudes of line width, hence varying the size and region of ion implantation.
Yet another object of the present invention is to provide an LDD method of simple fabrication process so that the organic polymer as a covering layer is simple to use and can be easily removed.
Additionally, the present invention can directly perform ion implantation of LDD to the berry diffusion (BD) layer of a mask ROM. This is also an object of the present invention.
To achieve the above objects, in the present invention, a patterned photo resist is first formed on a silicon substrate. Shallow ion implantation is then performed to the silicon substrate to form a shallowly doped layer. Next, a covering layer of organic polymer covers on the photo resist. Deep ion implantation of high dose is then performed to the silicon substrate to form a deeply doped layer as a drain and a source. Finally, after the covering layer and the photo resist are removed, a poly gate is formed on the silicon substrate.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:
REFERENCES:
patent: 6103137 (2000-08-01), Park
Macronix International Co. Ltd.
Rosenberg , Klein & Lee
Tsai Jey
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