Method of fabricating gate

Details Method of fabricating gate Method of fabricating gate

2000-11-30

2002-10-01

Niebling, John F. (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S637000, C438S700000, C438S734000, C438S066000, C438S270000

Reexamination Certificate

active

06458657

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89119720, filed Sep. 25, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a fabrication method and a structure of a gate. More particularly, this invention relates to a method to increasing the effective surface of the dielectric layer between a floating gate and a control gate.
2. Description of the Related Art
Stacked-gate non-volatile memory devices such as erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory, have attracted great attention and research due to excellent data storage properties without the additional applying electric field.
The current-voltage (I-V) characteristics of the stacked-gate non-volatile memory devices can be derived by the I-V characteristics of the conventional metal-oxide semiconductor (MOS) device and the capacitive coupling effect. Normally, the higher the capacitive coupling effects a device has, the lower operatioin voltage is required.
FIG. 1
shows a structure of a conventional stacked-gate non-volatile flash memory after forming and patterning conductive layers
26
and
50
. The conductive layers
26
and
50
construct a floating gate. A dielectric layer
24
is formed as the gate dielectric layer between the substrate and the floating gate. In
FIG. 1B
, a dielectric layer
52
is formed on the floating gate, and a control gate is formed on the dielectric layer
52
. The control gate comprises a conductive layer
54
. Both
FIGS. 1A and 1B
have a gate
58
and a non-gate region
60
. The conductive layers
26
and
50
in the non-gate region
60
are removed while patterning the dielectric layer
52
and the conductive layer
54
.
FIG. 2
shows a cross sectional view along the cutting line II—II as shown in
FIGS. 1A and 1B
. In
FIG. 2
, a gate is formed on a substrate comprising a semiconductor substrate
20
, a source region
22
and a drain region
23
. The gate comprises the gate dielectric layer
24
, the conductive layers
26
and
50
, the dielectric layer
52
and the conductive layer
54
.
The conventional stacked-gate non-volatile flash memory comprises four junction capacitors. They are C
FG
between the floating gate (the conductive layers
26
and
50
) and the control gate (the conductive layer
54
), C
B
between the floating gate and substrate
20
, C
S
between the floating gate and the source region
22
, and C
D
between the floating gate and the drain region
23
.
The capacitive coupling ratio can be represented by:
Capacitive
⁢
 
⁢
coupling
⁢
 
⁢
ratio
=
C
F
⁢
 
⁢
G
C
F
⁢
 
⁢
G
+
C
B
+
C
S
+
C
D
From the above equation, when the junction capacitor C
FG
increases, the capacitive coupling ratio increases.
The method for increasing the junction capacitance C
FG
includes increasing the effective surface of the dielectric layer between the floating gate and the control gate, reducing the thickness of the dielectric layer and increasing the dielectric constant (k) of the dielectric layer.
The dielectric layer between the floating gate and the control gate requires a sufficient thickness to prevent the electrons within the floating gate from tunneling to the control gate during operation to cause device failure.
The increase of the dielectric constant involves the replacement of fabrication equipment and a further advance fabrication technique, so that it is difficult to achieve.
Therefore, to increase the effective surface of the dielectric layer betweent eh floating gate and the control gate becomes a trend for increasing the capacitive coupling ratio.
In
FIG. 2
, in the conventional stacked-gate non-volatile memory, the dielectric layer
30
encircles the conductive layer
26
. That is, the conductive layer
26
is formed in an opening
44
of the dielectric layer
30
, while the surface level of the dielectric layer
26
is higher than the surface level of the conductive layer
26
. Therefore, the upper portion of the opening
44
is not filled with the conductive layer
26
. Instead, the upper portion of the opening
44
is filled with the conformal conductive layer
50
. Being conformal to the dielectric layer
30
with the recess of the upper portion of the opening
44
, the conductive layer
50
has a recess to result in an additional effective surface of the dielectric layer
52
formed subsequently. However, thus formed, the vertical thickness of the dielectric layer
52
is increased.
Referring to
FIGS. 1A
,
1
B and
2
, when the dielectric layer
52
and the conductive layer
54
are patterned, the dielectric layer
52
, the conductive layer
54
, the conductive layers
50
and
26
in the non-gate region are removed. As the conductive layer
50
has a recess, the vertical thickness of the dielectric layer
52
is far larger than the lateral thickness to cause great difficulty in etching, or even cause the dielectric layer residue. As a result, though the effective surface of the dielectric layer is increased, it is difficult to remove the dielectric layer
52
in the non-gate region
60
. To remove the dielectric layer
52
completely, the depth of the recess has to be reduced. In this case, the effective surface is reduced.
The signal storage of the dynamic random access memory is performed by selectively charging or discharging the capacitors on the semiconductor surface. The reading or writing operation is executed by injecting or ejecting charges from the storage capacitor connected to a transfer field effective transistor.
The capacitor is thus a heart of a dynamic random access memory. When the surface of the memory cell is reduced, the capacitance is reduced to seriously affect the stack density of the memory. As a consequence, the read-out performance is degraded, the occurrence of soft errors is increased, and the power consumption during low voltage operation is increased. Increasing the surface area of the dielectric layer between the bottom and top electrode becomes one effective method to resolve the above problems. However, additional photomasks are required for achieving such goal, the fabrication cost is thus increased.
SUMMARY OF THE INVENTION
The invention provides a fabrication method and structure of a gate to increase the effective surface between the floating gate and the control gate of the gate. In addition, the vertical etching thickness of the dielectric layer is reduced.
In the method of fabricating a gate, a gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different etching rates are formed to cover the upper portion of the floating gate and the first dielectric layer. Using an etching mask, an opening is formed within the second dielectric layer to expose the floating gate and a portion of the second dielectric layers by performing an anisotropic etching process. Using the same etching mask, the second dielectric layers exposed within the opening is further etched by performing an isotropic etching process. Due to the different etching rates, a dielectric layer with an uneven and enlarged surface is formed. A conformal conductive layer is formed on the exposed lower portion of the floating gate and the exposed second dielectric layers as an upper portion of the floating gate. A conformal third dielectric layer is formed on the conformal conductive layer, followed by forming a control gate on the third dielectric layer.
In the above method, as the anisotropic and isotropic etching processes are performed using the same etching mask, the total number of photomasks is thus reduced. In addition, due to the different etching rates of the second dielectric layers, the opening with stair-like profile is formed. That is, the second dielectric layers exposed in the opening have a stair-like profile, therefore, the conformal conductive layer and the conformal third dielectric layer also have the stair-lik

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