Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-10
2002-11-26
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S319000, C257S321000, C438S266000, C438S201000, C438S211000, C438S257000
Reexamination Certificate
active
06486508
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a fabricating method thereof, and more particularly to a non-volatile semiconductor memory device and a fabricating method thereof, which prevents mismatching between a split floating gate and a control gate, so that there will be no different characteristics of memory cells in response to odd/ even numbered word line.
2. Description of the Prior Art
In general, a non-volatile semiconductor memory device has recently shown a tendency to be widely used in a variety of fields since it can not only erase/store data with electrical connection, but also store data without supply of electricity. These memory cells of the non-volatile semiconductor memory device are classified into NAND type and NOR type.
There are different advantages in those NAND and NOR types of memory cells in response to the trend of becoming high integration and high speed of memory cells, so that they have been increasingly used in a variety of applications to make the best use of those advantages of respective types.
The NOR type of the non-volatile semiconductor memory device comprises a plurality of memory cells having a transistor at a bit line connected in parallel and only one memory cell transistor positioned between a drain connected to the bit line and a source connected to a common source line. There is an advantage in the NOR type of a non-volatile semiconductor memory device in that the current of memory cells is high enough to operate at high speed, but a disadvantage in that it is difficult to have a high integration due to large area taken by the contact of bit lines and source lines.
The NOR type of the non-volatile memory device is constructed in a deposition structure in which a floating gate and a control gate are deposited with an insulation interlayer therebetween, and the processes thereof will be described below.
First of all, in programming data, when voltage is applied to the bit line and the control gate connected with the drain of memory cells, electric current flows between the source and the drain, so that electrons are injected into the floating gate by a channel hot electron injection mechanism. As a result, data are programmed.
In erasing, when voltage is applied to a source, electrons are flown out of the floating gate by a Fowler-Nordheim tunneling mechanism. As a result, data are erased.
In reading, when adequate voltage is applied to the bit line and the control gate of the selected memory cells, the presence of current at the selected memory cell transistor is read. As a result, data are read.
As memory cells are connected in parallel to the bit line in the non-volatile memory device, if the threshold voltage of the memory cell transistor gets lower than the voltage (usually 0V) applied to the control gate of the not-selected memory cells, current flows between the source and the drain, regardless of the ON/OFF state of the selected memory cells, an operational failure (wrong operation) occurs that all the memory cells may be read as the ON state thereof. Thus, there is a difficulty in the nonvolatile memory device that the threshold voltage should be strictly controlled. Also, because excessive amount of current flows at the memory cells in programming data by the channel hot electron injection mechanism, a high capacity of the pump may be required for generating the voltage in programming data.
In order to solve the aforementioned problem, the non-volatile semiconductor memory devices in a variety of structures, commonly called a split gate type, have been suggested. A representative example of all has been disclosed in U.S. Pat. No. 5,045,488 titled as a “METHOD OF MANUFACTURING A SINGLE TRANSISTOR NON-VOLATILE, ELECTRICALLY ALTERABLE SEMICONDUCTOR MEMORY DEVICE.”
As shown in
FIGS. 1 through 3
, the non-volatile semiconductor memory device disclosed therein comprises: an active area
11
of a substrate
10
isolated by a field insulating layer
13
; a pair of floating gates
15
arranged at a first gate insulating layer of the active area
11
with a source area
17
therebetween; an oxide layer
19
positioned at the floating gates
15
; second gate insulating layers
21
positioned at the lateral surfaces of the floating gates
15
to be used for tunneling in erasing data; and control gates
23
simultaneously overlapping an external side of the floating gates
15
, the second gate insulating layer
21
and a part of the drain area
18
, that is, extensively from an external portion of the floating gate
15
to a part of the drain area
18
. An interlayer
25
is deposited at the aforementioned structure, and a bit line
27
is formed for electrical connection through a contact hole
26
to the drain area
18
.
At this time, the channel areas formed by the floating gates
15
and the control gates
23
are connected in series. The area marked with a dot line represents a unit cell area (UCA). L
1
and L
2
respectively symbolize gate lengths of selected memory cell transistors. Even if only a pair of floating gates corresponding to an active area
110
are shown in the drawings for convenient description, it should be taken for granted that a number of pairs of floating gates are repeatedly arranged correspondingly to the active areas
110
in actuality.
Operation of the conventional non-volatile semiconductor memory device thus constructed will be described below. First of all, in programming data, if a high voltage is applied to the source area
17
of the UCA, the floating gate
15
is induced into a predetermined voltage by a coupling phenomenon. Then, if a voltage, for example, higher than the threshold voltage of the transistor formed by the control gate and the channel formed by the floating gate
15
is applied to the control gate
23
, current flows between the source area
17
and the drain area
18
. At this time, the channel hot electron injection mechanism is performed, so that electrons are injected into the floating gate
15
. As a result, data is programmed.
Therefore, if voltage applied to the control gate
23
is properly controlled, hot electrons can be formed at a lower end of the floating gate
15
and the electric field gets strong enough to improve the data programming efficiency. In addition, the current flowing between the source area
17
and the drain area
18
can also be restricted to reduce power consumption, thereby no longer requiring a high capacity of a pump to be used at the stacked NOR type of the non-volatile memory device.
In erasing data, if a high voltage is applied to the control gate
23
, the electrons collected at the floating gate
15
are flown out through the second gate insulating layer
21
by the electric field formed between the control gate
23
and the floating gate
15
. As a result, data are erased.
In reading data, if a predetermined voltage is applied to the bit line
27
and the control gate
23
connected with the drain area
18
of the memory cells, data can be read in accordance with the presence of the current flowing between the memory cells. At this time, if the channel area formed by the control gate
23
and the channel formed by the floating gate
15
are all made, that is, if voltage, higher than the threshold voltage, is applied to the gate, the non-volatile memory cells flow current.
In general, the select transistors of the memory cells are manufactured to have threshold voltage (Vth) of approximately 1.0V. The floating gate
15
has a high threshold voltage at the data programmed memory cells and a low threshold voltage at the data erased memory cells including −Vth sometimes. However, in case that the floating gate
15
has −Vth due to over-erasure, the select transistor having a threshold voltage of approximately 1.0V turns off the channel even if 0V is applied to the control gate
23
. Therefore, there will be not problem of over-erasure any longer. In this way, even if the threshold voltage of the floating gate of the NOR type of the non-volatile s
Flynn Nathan J.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Wilson Scott R
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