Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-13
2002-06-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S275000, C438S279000
Reexamination Certificate
active
06403417
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for integrating the process of manufacturing an embedded memory and the process of manufacturing a landing via and a strip contact in the embedded memory, and more particularly, to a method for decreasing the occupied space of a strip contact in a memory device.
DESCRIPTION OF THE PRIOR ART
Due to continued improvement in process integration, it is the present trend of the semiconductor industry to fabricate semiconductor integrated circuits that integrate both a memory cell array and high-speed logic circuit elements onto a single chip to form an embedded memory. The embedded memory simultaneously combines the memory arrays and logic circuits to greatly reduce the circuit area and to increase signal processing speed. To avoid short-circuiting of various devices in the embedded memory, after the formation of MOS transistors an insulation layer is formed and covers the surface of the semiconductor wafer. Then, a photo-etching-process (PEP) is used to form a plurality of contact holes. A conductive layer is filled into the contact holes to allow for electrical connection of each metal-oxide-semiconductor (MOS) transistor with the circuit.
Please refer to
FIG. 1
to FIG.
11
.
FIG. 1
to
FIG. 11
are cross-sectional diagrams of a prior art method for manufacturing a metal-oxide-semiconductor (MOS) transistor of an embedded memory on a semiconductor wafer
10
. As shown in
FIG. 1
, the surface of the silicon substrate
12
is divided into a memory array area
14
and a periphery circuit region
16
. The memory array area
14
contains a cell well
18
, and the periphery circuit region
16
contains at least one N-well
20
and at least one P-well
22
. Each region is separated by several shallow trench isolation structures
23
.
The prior art method first involves forming a gate oxide layer
21
, a polysilicon layer
24
, a polycide layer
26
and a cap layer
28
composed of silicon nitride, respectively, on the surface of the semiconductor wafer
10
. Then, as shown in
FIG. 2
, a photoresist layer
30
is formed above the cap layer
28
followed by the use of a lithographic process to simultaneously define gate patterns of the memory array area
14
and the periphery circuit region
16
in the photoresist layer
30
. Thereafter, the patterned photoresist layer
30
is used as a mask layer to perform an etching process for removing the cap layer
28
, the polycide layer
26
and the polysilicon layer
24
down to the surface of the gate oxide layer
21
so as to simultaneously form a plurality of gates
32
above the cell well
18
of the memory array area
14
and a plurality of gates
34
above both the N-well
20
and the P-well
22
of the periphery circuit region
16
.
As shown in
FIG. 3
, the photoresist layer
30
above the cap layer
28
is completely removed followed by performing an ion implantation process to form a doped region (not shown) on the surface of the silicon substrate
12
adjacent to the gates
32
,
34
. Thereafter, a rapid thermal process (RTP) is performed to drive dopants in the doped region into the silicon substrate
12
so as to form lightly doped drains (LDD)
36
of each MOS transistor.
As shown in
FIG. 4
, a silicon nitride layer (not shown) is deposited on the semiconductor wafer
10
followed by the use of an an-isotropic etching process to etch back portions of the silicon nitride layer to form a spacer
38
around each gate
32
,
34
of the memory array area
14
and the periphery circuit region
16
, respectively. Then, an ion implantation process is performed to form a source and drain of each MOS transistor in the periphery circuit region
16
. A photoresist layer (not shown) is first formed to cover the memory array area
14
and gates
32
,
34
of the N-well
20
. Then, N-type dopants are used to implant the surface of the P-well
22
so as to form a doped region
42
, followed by the removal of the photoresist layer. Next, another photoresist layer (not shown) is formed to completely cover the memory array area
14
and the gate
34
of the P-well
22
. Then, P-type dopants are used to implant the N-well
20
of the periphery circuit region
16
so as to form a doped region
40
. Thereafter, a rapid thermal process is used to drive dopants of each doped region
40
,
42
into the silicon substrate
12
so as to form the source and the drain of each MOS transistor in the periphery circuit region
16
.
As shown in
FIG. 5
, a salicide block (SAB) layer
44
is formed on the silicon substrate
12
of the memory array area
14
. Then, a self-aligned silicide process is performed in the periphery circuit region
16
for forming a salicide layer
46
on the surface of each source and drain so as to finish the process of manufacturing a MOS transistor of an embedded memory according to the prior art.
After the formation of the MOS transistor of an embedded memory, a landing via and a local interconnection of the embedded memory are formed on the semiconductor wafer
10
. As shown in
FIG. 6
, a dielectric layer
48
, such as a silicon oxide layer, is first formed on the surface of the semiconductor wafer
10
. A photolithographic process is then used to define a landing via hole
50
and contact holes
51
a,
51
b
in the dielectric layer
48
, as shown in FIG.
7
. The contact hole
51
a
connects to the gate of MOS transistor
34
and the contact hole
51
b
connects to a source or drain of another MOS transistor. Therefore, contact holes
51
a,
51
b
are not located on the same vertical cross section.
As shown in
FIG. 8
, a glue layer or barrier layer
52
and a metal layer
54
are formed, respectively, on the silicon substrate
12
and fill both the landing via hole
50
and the contact holes
51
a,
51
b.
The glue layer or barrier layer
52
and the metal layer
54
are, respectively, composed of titanium, or titanium nitride and tungsten metal. Thereafter, as shown in
FIG. 9
, the dielectric layer
48
is used as an etching stop layer for chemical mechanical polishing (CMP) of the metal layer
54
so as to form a landing via
55
and contact plugs
56
a,
56
b.
Next, as shown in
FIG. 10
, a metal conductor layer
57
is formed on the semiconductor wafer
10
, followed by the formation of a patterned photoresist layer
58
on the metal conductor layer
57
to define patterns of metal conductors. The metal conductor layer
57
is composed of aluminum (Al), copper (Cu) or aluminum copper alloy. Finally, as shown in
FIG. 11
, an etching process is performed to remove the metal conductor layer
57
not covered by the photoresist layer
58
so as to form metal conductors
59
a,
59
b
connecting to the landing via
55
and contact plugs
56
a,
56
b,
respectively. The metal conductor
59
b,
electrically connects the gate of the MOS transistor
34
with a source or drain of another MOS transistor, and together with the contact plugs
56
a,
56
b
forms a local interconnection.
However, in the disclosure of the prior art method for fabricating an embedded memory, in order to simultaneously form gates in both the periphery circuit region and the memory array area, the electrical properties of the periphery circuit region is taken into account whereby a polycide layer is directly deposited on the polysilicon layer for reducing the resistance of the gate structure in the periphery circuit region. A self-aligned silicide operation is also used to form a salicide layer on each source and drain for reducing the contact interface resistance of the MOS transistors. Generally speaking, the polycide layer formed by deposition has a greater resistivity than that of the salicide layer. Hence, the electrical performance of the gate structure composed of both the polycide layer and a cap layer in the periphery circuit region differs with that of the gate structure composed of the salicide layer in the conventional periphery circuit region to result in the unfitness of the cell library established by logic circuits. Secondly, after the formation of the MOS transistor of an emb
Chien Sun-Chieh
Kuo Chien-Li
Hsu Winston
Kennedy Jennifer M.
Niebling John F.
United Microelectronics Corp.
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