Semiconductor device having field effect transistors...

Details Semiconductor device having field effect transistors... Semiconductor device having field effect transistors...

2000-07-12

2002-11-26

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S218000, C438S231000, C438S595000

Reexamination Certificate

active

06486012

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor device and, more particularly, to a semiconductor device having an n-channel type field effect transistor and a p-channel type field effect transistor different in thickness of the gate electrodes and a process of fabrication thereof.
DESCRIPTION OF THE RELATED ART
The integration density of the semiconductor device has been increased, and miniaturization of circuit components allows the manufacturer to increase the integration density. One of the most important circuit components is a field effect transistor, and shallow source and drain regions and a thin gate insulating layer are indispensable for the miniature field effect transistor.
Field effect transistors are broken down into two categories. The first category is featured by a surface channel structure, and the second category is featured by a buried-channel structure. When an enhancement type field effect transistor creates a conductive channel identical in conductivity type with the gate electrode, the enhancement type field effect transistor is categorized into the first category. If a surface channel type field effect transistor has an n-type gate electrode, the surface channel type field effect transistor inverts the channel region to the n-type. On the other hand, if a surface channel type field effect transistor has a p-type gate electrode, the channel region is inverted to the p-type so as to flow drain current therethrough. The surface channel structure is suitable for the miniaturization of the field effect transistor.
The buried channel structure is disadvantageous to the miniaturization. Presently, it is impossible to employ the buried channel structure in a semiconductor device designed on the basis of quarter-micron design rules. A p-channel buried channel structure type field effect transistor has a boron-doped buried layer under an n-type doped polysilicon, and the boron-doped buried layer should be as shallow as possible against the punch-through phenomenon. However, the boron is rapidly diffused, and the boron-doped buried channel tends to be deep. Thus, the buried channel structure is disadvantageous to the miniature field effect transistor with a short channel.
The fabrication process is different between the surface channel type field effect transistor and the buried channel type field effect transistor. For example, dopant impurity is usually ion introduced into the gate electrode of the surface channel type field effect transistor during the ion-implantation into surface regions on both sides of the channel region, and, accordingly, the gate electrode and the source/drain regions are doped with the same dopant impurity. On the other hand, a dopant impurity is diffused from a phospho-glass into the gate electrode of the buried channel type field effect transistor. If a p-channel type field effect transistor and an n-channel type field effect transistor are fabricated on a semiconductor substrate, the dopant impurity is concurrently driven into both gate electrodes.
FIGS. 1A
to
1
E illustrates a typical example of the process of fabricating a surface channel type complementary transistor. An n-channel type field effect transistor
1
and a p-channel type field effect transistor
2
form in combination the surface channel type complementary transistor.
The prior art process starts with preparation of a silicon substrate
3
. A thick field oxide
4
a
is selectively grown on the major surface of the silicon substrate
3
by using the LOCOS (local oxidation of silicon) technology, and separates the major surface into a plurality of active areas.
FIGS. 1A
to
1
E show two active areas, and the two active areas are assigned to the n-channel type field effect transistor
1
and the p-channel type field effect transistor
2
, respectively.
The right active area is covered with a photo-resist ion-implantation mask (not shown), and boron is ion implanted into the left active area for forming a p-type well
3
a.
The ion-implantation is repeated under different conditions. The boron is firstly accelerated under 300 KeV at dose of 1×10
13
cm
−2
, thereafter, under 150 KeV at dose of 3×10
12
cm
−2
and under 40 keV at dose of 7×10
12
cm
−2
.
The photo-resist ion-implantation mask is stripped off, and, thereafter, the left active area is covered with another photo-resist ion-implantation mask (not shown). Phosphorous or arsenic is repeatedly ion implanted into the right active area. If the phosphorous is used, the first ion-implantation is carried out under the acceleration energy of 700 KeV at dose of 1.33×10
13
cm
−2
, thereafter, the acceleration energy and the dose are changed to 300 KeV and 4×10
12
cm
−2
, and, finally, the ion-implantation is carried out under the acceleration energy of 60 KeV at dose of 5×10
12
cm
−2
. The photo-resist ion-implantation mask is stripped off, and the ion-implanted phosphorous forms an n-type well
3
b
as shown in FIG.
1
A.
Subsequently, the silicon substrate
3
is placed in high-temperature dry oxidation ambience. The surface of the p-type well
3
a
and the surface of the n-type well
3
b
are thermally oxidized at 850 degrees in centigrade, and the p-type well
3
a
and the n-type well
3
b
are covered with thin gate oxide layers
1
a
and
2
a
of 6 nanometers thick, respectively.
Subsequently, polysilicon is deposited to 150 to 200 nanometers thick over the entire surface of the semiconductor structure by using a chemical vapor deposition, and the thin gate oxide layers
1
a
/
2
a
are covered with a polysilicon layer. In this instance, silane or disilane is introduced into a reaction chamber where the silicon substrate
3
is placed, and is decomposed at 650 degrees in centigrade. The silicon layer is intentionally undoped.
Photo-resist solution is spread over the undoped polysilicon layer, and is baked so as to form a photo-resist layer. A pattern image for gate electrodes is optically transferred from a photo-mask (not shown) to the photo-resist layer by using ultra-violet light or excimer laser light, and a latent image is formed in the photo-resist layer. The photo-resist layer is patterned into a photo-resist etching mask
5
a
through a development of the latent image.
The undoped polysilicon is patterned into gate electrodes
1
b
/
2
b
by using a dry etching technique. The gaseous etchant has a large selectivity between the undoped polysilicon and the silicon oxide, and the thin gate oxide layers
1
a
/
1
b
are not damaged. The resultant structure after the dry etching is shown in FIG.
1
B. The photo-resist etching mask
5
a
is stripped off.
Subsequently, silicon oxide is deposited to 100 to 150 nanometers thick over the entire surface of the resultant structure by using a chemical vapor deposition. Silane and oxygen are introduced into a reaction chamber where the silicon substrate
3
is placed, and the silicon oxide is produced at 800 degrees in centigrade. The silicon oxide layer topographically extends over the thin gate oxide layers
1
a
/
2
a
and the undoped polysilicon gate electrodes
1
b
/
2
b.
The silicon oxide layer is anisotropically etched by using a plasma etching system, and side wall spacers
1
c
/
2
c
are left on both sides of the gate electrodes
1
b
/
2
b
as shown in FIG.
1
C.
Subsequently, silicon oxide is deposited to 5 to 10 nanometers thick over the entire surface of the resultant structure shown in
FIG. 1D
, and a thin silicon oxide layer
4
b
topographically extends. The p-type well
3
a
is covered with a photo-resist ion-implantation mask (not shown), and arsenic is ion implanted into the n-type well
3
a
at dose of 5×10
15
cm
−2
under the acceleration energy of 50 KeV. The arsenic is introduced into the p-type well
3
a
and the gate electrode
1
b
, and forms n-type source/drain regions
1
d
/
1
e.
The ion-implantation mask is stripped off, and the n-type well
3
b
is covered with another photo-resist ion-implantation mask (not shown). Boron fluoride (BF

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