Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-12
2002-12-10
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S307000, C438S655000
Reexamination Certificate
active
06492236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
A mask-offset drain (offset region is also formed in the source side in some cases) structure has been known as one of conventional high withstand voltage (about 10 V) MOS transistor structures. This structure is characterized in that a low concentration drain region (offset drain region) having a relatively long distance of about 0.5 to 1.0 ìm is provided near the gate electrode by using a photo mask, with the result that an electric field is relaxed to attain a higher withstand voltage. Further, an overlap capacitance between the gate and the drain is small. As a result, a gate charging speed is high in the case where this structure is used for a circuit, so that the mask-offset drain structure is suit able high-speed operation. Further, a drain impurity concentration in the offset region is low, so that a depletion layer can be extended, with the result that a drain withstand voltage can be increased. At this time, since a length L of the transistor can be shortened, it is suitable as an element having high driving power and a high withstand voltage.
On the other hand, with respect to a fine MOS transistor having a slightly low voltage range of about 5 V, a transistor of an LDD structure including source and drain regions each having a low impurity concentration, which are called LDDS, is known. The source and drain regions each having a low impurity concentration are defined in a self-alignment manner with respect to the gate electrode by side spacers and the length thereof is about 0.1 to 0.2 &mgr;m.
In the case of the transistor of the LDD structure, a homopolar gate and high-melting metallic silicide (including self-aligning silicide) can be also achieved as means for further improving the performance of the transistor.
However, when adopting a homopolar gate structure and a high-melting metallic silicide structure for the MOS transistor having the mask-offset drain structure, which is suitable for an application in which a withstand voltage is required, there arises a problem such that, since it is necessary to form low concentration drain regions having a distance longer than that required in the MOS transistor having the LDD structure, the entire processing steps become very complicated.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problem, and an object of the present invention is to provide a manufacturing method capable of obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance.
In order to achieve the above-mentioned object, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized by comprising the steps of: patterning a gate electrode formed on a thin insulating film on a silicon substrate, into a predetermined shape and then forming source and drain regions having a relatively low concentration by an ion implantation method using the gate electrode as a mask; forming a thick insulating film on the gate electrode, thickly applying a positive resist onto an entire surface of the thick insulating film, and then exposing the positive resist at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developing the exposed positive resist; etching the thick insulating film by an amount substantially corresponding to a film thickness thereof by anisotropic etching, using those portions of the positive resist partially remaining in a step portion as a mask; removing the remaining portions of the positive resist and then introducing an impurity having a high concentration into the gate electrode and the source and drain regions of an MOS transistor using a remaining portion of the thick insulating film as a mask; and then forming a silicide layer on exposed portions of the gate electrode and the source and drain regions of the MOS transistor, respectively, to thereby obtain a high-melting metallic silicide structure.
According to the present invention, there is provided a method of manufacturing a semiconductor device, by which it is capable of obtaining an MOS transistor having low concentration drain regions with a long distance, by a simple method and at a low cost.
REFERENCES:
patent: 6180477 (2001-01-01), Liao
patent: 6291354 (2001-09-01), Hsiao et al.
patent: 6316319 (2001-11-01), Ishida et al.
patent: 6383906 (2002-05-01), Wieczorek et al.
patent: 6399451 (2002-06-01), Lim et al.
Osanai Jun
Takasu Hiroaki
Adams & Wilks
Chaudhari Chandra
Seiko Instruments Inc.
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