Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-10-02
2002-06-11
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S723000, C438S299000, C438S738000, C438S633000
Reexamination Certificate
active
06403424
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a manufacturing process of non volatile read only memory, and especially to a method for forming self-aligned read only memory code implanting area and metal word line by dual damascene trenches.
BACKGROUND OF THE INVENTION
In the mask read only memory, a field effect transistor is used as a memory cell. Memory cells are arranged as an array in a memory. The assembly of each column and row represents a specific memory cell address. The open or close of the memory cell is determined by the values of the gate voltage with a voltage threshold.
The manufacturing process of a general mask read only memory contains the steps of multiple depositions, lithography, and etchings. In the lithography, the pattern on the mask is completely transferred to the photoresistor on the surface of a substrate so that the succeeding etching or ion implantation or other processes can be made conveniently. The completed mask read only memory has a structure of a plurality of polysilicon word lines crossing over the bit lines. The channels of the memory cells are between the areas blow the covering area of the word lines and the bit lines so that in the programming process, the ion implantation is selectively performed to the surface of the channel area to change the ion distribution in the channel area. Thus, voltage threshold is adjusted for storing data.
However, with the increment of the integration in the semiconductor, the design rule becomes small so that the size of element must be reduced. In the programming ion implantation in the channel area, the mask read only memory is easily disalignment in the ion implantation area due to the patternized photoresistor in the lithography process, causing the voltage threshold shift of the element so that the directions of the word lines and bit lines are shifted. Further, the data in memory cell of the read only memory is wrong and peripheral other implantation area is interfered, thereby effecting the operation property of the whole memory.
In the prior art, phase shift mask (PSM) is used to resolve this problem. However, the technology of PSM is hard and is not economical.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the present invention is to provide a method for forming a self-aligned mask read only memory by dual damascene trenches, wherein the manufacturing range in the lithography is enlarged and an ion implantation process with self-aligned ability is complete. Therefore, self-aligned read only memory codes and metal word lines are formed. The defect of disalignment in the read only memory code is resolved and the difficulty in the manufacturing process is reduced.
Another object of the present invention is to provide a method for forming a self-aligned mask read only memory by dual damascene trenches which can be used in the MROM process of below 0.18 &mgr;m. The manufacturing process of the present invention is simple and the metal gate and word line can be formed at the same time.
A further object of the present invention is to provide a method for forming a self-aligned mask read only memory by dual damascene trenches, wherein metal word line is used to replace the prior art polysilicon word line to reduce the resistance of the word line, save power and cost.
To achieve the object, the present invention provides a method for forming a self-aligned mask read only memory by dual damascene trenches comprising the steps of: forming a gate oxide layer on a substrate and a defined first polysilicon layer; doping the substrate by using the first polysilicon layer as a mask so as to be formed with a buried bit line; depositing a first oxide layer and removing part of the first oxide layer until the first polysilicon layer is exposed; forming a patternized second polysilicon layer on the substrate to cover part of the first polysilicon layer and part of the first oxide layer; removing the first polysilicon layer and the first oxide layer by using the second polysilicon layer as a mask; depositing a second oxide layer on the substrate, and removing part of the second oxide layer until the second polysilicon layer is exposed; removing the second polysilicon layer and part of the first polysilicon layer so as to be formed with dual damascene trenches; forming a first patternized photo resistor on the substrate to cover part of the first polysilicon layer; using the first patternized photo resistor as a mask to perform ion implantation process; and forming a self-aligned first ion doping area blow the exposed first polysilicon layer; removing the first patternized photo resistor; forming a second patternized photo resistor on the substrate to cover part of the first polysilicon layer; using the second patternized photo resistor as a mask to perform a second ion implantation and forming a self-aligned second ion doping area on the substrate below the first polysilicon layer; removing the second patternized photo resistor; and depositing a metal layer to fully fill the dual damascene trenches on the substrate; filling fully the dual damascene trenches so as to be formed with metal gate and word lines.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.
REFERENCES:
patent: 6265319 (2001-07-01), Jang
Chung Henry
Jeng Pei-Ren
Lee Chung-Yeh
Chaudhuri Olik
Huynh Yennhu B.
Macronix International Co. Ltd.
Rosenberg , Klein & Lee
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