Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-17
2002-02-05
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S587000, C438S595000
Reexamination Certificate
active
06344398
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming different transistor devices for mixed-mode IC, and more particularly to a method for forming transistor devices with different spacer width for mixed-mode IC.
2. Description of the Prior Art
The conventional mixed-mode IC includes embedded dynamic random access memory (embedded DRAM), embedded static random access memory (embedded SRAM) and application specific integrated circuit (ASIC). In a mixed-mode IC, there are at least two types of transistor devices, for example, memory devices and logic devices. However, different transistor devices are supplied with different operational voltages of V
DD
. The higher the operational voltage V
DD
is, the higher the driving current I
dsat
between the source and the drain terminal. In the mixed-mode IC, each transistor device has its own spacer structure whose width varies according to the design rule. The spacer is a means to provide a suitable resistance for the transistor channel. As shown in
FIG. 1
, if the width L of the spacer
1
is too short, the electric field of the lightly doped drain (LDD) region
2
is significantly increased, and thus the hot carrier effect or other short channel problem is made more severe, even through the driving current I
dsat
is also increased. Therefore, this leads to the failure of device reliability. However, if the spacer width is too long, the hot carrier effect is eliminated, while the driving current between the source and the drain terminal will be too low. Hence, there is a trade-off between the high operational voltage V
DD
and the length of the spacer for transistor devices in the mixed-mode IC.
The main defect in the conventional method of spacer formation is that there is no systematic process for simultaneously forming spacers with different widths to satisfy the demands of the different types of transistor devices in the mixed-mode IC. Accordingly, there exists a desire to provide an improved method for simultaneously forming spacers with different width.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a method for forming transistor devices with different spacer widths for mixed-mode IC, in which at least three kinds of different transistor devices are formed on a wafer. Two of them have their own spacer with different widths, and the remaining one is without a spacer.
It is another object of the present invention to provide a method for forming transistor devices with different spacer width for mixed-mode IC, which utilizes a two-step etching process.
In order to achieve the above objects, the present invention provides a method for forming transistor devices with different spacer width for mixed-mode IC. Firstly, a semiconductor substrate is provided with at least a first conductive gate, a second conductive gate and a third conductive gate formed thereon. A lightly doped drain (LDD) region is formed under each side of the first conductive gate and the second conductive gate in the substrate. Then, a first oxide layer is formed over the first conductive gate, the second conductive gate and the third conductive gate, and a first etch operation is performed to form an oxide spacer along each sidewall of the first conductive gate, the second conductive gate and the third conductive gate. Thereafter, a first mask is formed over the first conductive gate, while exposing the second conductive gate and said third conductive gate. Subsequently, the oxide spacer is removed along each sidewall of the second conductive gate and the third conductive gate, and then the first mask is removed over the first conductive gate. Afterwards, a silicon nitride layer is formed over the first conductive gate with the oxide spacer formed along each sidewall thereof, the second conductive gate and the third conductive gate, wherein the thickness of the silicon nitride layer is different from that of the first oxide layer. Then, a second etch operation is performed to form a spacer of silicon nitride along each sidewall of the second conductive gate and the third conductive gate. After that, a second conformal oxide layer is formed over the first conductive gate, the second conductive gate and the third conductive gate. Then, a second mask is formed over the second conformal oxide layer formed on the second conductive gate, while exposing the second conformal oxide layer over the first conductive gate and the third conductive gate. Subsequently, the second conformal oxide layer is removed over the first conductive gate and the third conductive gate, and then the second mask is removed over the second conformal oxide layer formed on the second conductive gate. Thereafter, the spacer of silicon nitride formed along each sidewall of the third conductive gate is removed. Finally, a source/drain region is formed in the substrate beside each of the lightly doped drain regions and each side of the third conductive gate.
REFERENCES:
patent: 5021354 (1991-06-01), Pfiester
patent: 5552331 (1996-09-01), Hsu et al.
patent: 5882973 (1999-03-01), Gardner et al.
patent: 6046089 (2000-04-01), Gardner et al.
patent: 6103611 (2000-08-01), En et al.
patent: 6248623 (2001-06-01), Chien et al.
Dang Trung
United Microelectronics Corp.
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