Method of forming a lower storage node of a capacitor

Details Method of forming a lower storage node of a capacitor Method of forming a lower storage node of a capacitor

2001-08-30

2002-08-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S398000, C438S964000

Reexamination Certificate

active

06432772

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method for forming a lower storage node of a capacitor.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is a collection of a large number of memory cells. Each memory cell comprises a metal oxide semiconductor (MOS) transistor and a capacitor in series. The capacitor design of the memory cell involves the formation of two node layers on a semiconductor wafer. One of the node layers is used as an upper field plate, and the other is used as a lower storage node. A cell dielectric layer is installed between them to isolate these two node layers. When a voltage is applied to one of the node layers, the voltage induces a corresponding charge on the other node layer. This charge is used to store and retrieve memory data.
Please refer to FIG.
1
.
FIG. 1
is a schematic diagram for forming a lower storage node
20
of a stack crown capacitor on a semiconductor wafer
10
according to the prior art. The semiconductor wafer
10
comprises a substrate
12
, an isolation layer
14
covering the substrate
12
, and a conductive layer
16
installed in the isolating layer
14
. The conductive layer
16
is made of doped polysilicon or amorphous silicon. The conductive layer
16
is used to electrically connect to a drain of the MOS transistor (not shown) on the substrate
12
, serving as a node contact. The conductive layer
16
is level with the isolation layer
14
.
In the prior art method of forming the lower storage node
20
of the capacitor, a dielectric layer
17
is formed on the isolating layer
14
. A lithography process is then performed to define the position of the lower storage node
20
using a photoresist layer (not shown). A dry etching process is performed to remove the portion of the dielectric layer
17
that is not covered by the photoresist layer until the surface of the isolating layer
14
is reached, forming a vertical hole
19
. Next, a low pressure chemical vapor deposition (LPCVD) process and a planarization process are performed to form an amorphous silicon (&agr;-Si) layer
18
(a portion of which is shown in
FIG. 1
) that covers the dielectric layer
17
and the walls and bottom of the hole
19
in order to form the initial lower storage node
20
of a capacitor in a memory cell.
Silane (SiH
4
) and SiH
2
Cl
2
(dichlorosiliane) gases are input for seedingin order to perform a hemi-spherical grain (HSG) process on the surface of the lower storage node
20
. The HSG process is used to transform the surface of the lower storage node
20
into a rough surface having a plurality of hemispherical grains, thereby increasing the surface area of the lower storage node
20
to double the original surface area. An ion implantation process can be performed when forming the amorphous silicon layer
18
, after completing the planarization process, or after the hemi-spherical process, in order to implant dopants into the surface of the amorphous silicon layer
18
for transformation into a doped amorphous silicon layer (doped &agr;-Si).
Please refer to FIG.
2
.
FIG. 2
is a schematic diagram that shows a collapse of the lower storage node
20
of the prior art capacitor. Because the amorphous silicon layer of the lower storage node
20
of the capacitor has a crown structure on the dielectric layer
14
, the thickness of the crown structure on the walls of the hole
19
is not large. Therefore, in subsequent semiconductor processes, especially in cleaning processes, the walls of the lower storage node
20
of the capacitor may easily collapse, which results in a reduced manufacturing yield.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a lower storage node of a capacitor to solve the problem of collapse, and further to increase the surface area of the lower storage node of the capacitor.
In the preferred embodiment of the present invention, the method involves first forming an isolation layer on the substrate of a semiconductor wafer, then forming at least one recess in the isolation layer by utilizing a photo-etching-process. Thereafter, a two stage in-situ doped deposition process is performed in order to form a first doped amorphous silicon (&agr;-Si) layer and a second doped amorphous silicon (&agr;-Si) layer, with a doping concentration of the second doped amorphous silicon (&agr;-Si) layer being less than that of the first doped amorphous silicon layer. A dielectric layer is formed to fill the recess, and a planarization process is performed in order to remove portions of the second doped amorphous silicon layer, the first doped amorphous silicon layer and the dielectric layer on the surface of the isolation layer. Finally, the dielectric layer and the isolation layer are removed, and a hemi-spherical grain (HSG) process is performed to form a rough surface with a plurality of hemispherical grains on the surface of the second doped amorphous silicon layer.
It is a feature of the present invention that the lower storage node of the capacitor comprises a first doped amorphous silicon layer with a high dopant concentration, and a second doped amorphous silicon layer with a low dopant concentration. The thickness of the lower storage node of the capacitor can thereby be controlled effectively, so as to avoid collapsing of the walls of the lower storage node of the capacitor in subsequent processes. The contact area of the lower storage node is increased due to the HSG process. Also, the boundary of the field plate does not exceed the width of the recess, which shrinks the spacing between the capacitor and other devices, and enhances integration. Additionally, in another embodiment of the present invention, the contact area for the lower storage node can be increased greatly by making a three-layered structure, which increases the charge carrying capacity (i.e., capacitance) of the capacitor.


REFERENCES:
patent: 5937314 (1999-09-01), Ping et al.
patent: 5963805 (1999-10-01), Kang et al.
patent: 6037219 (2000-03-01), Lin et al.
patent: 6046083 (2000-04-01), Lin et al.
patent: 6090679 (2000-07-01), Lou
patent: 6121084 (2000-09-01), Coursey
patent: 6174769 (2001-01-01), Lou

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