Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-29
2002-06-04
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S568000, C438S637000, C438S639000, C438S747000
Reexamination Certificate
active
06399480
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements for forming and insulating local interconnects within a semiconductor device.
BACKGROUND ART
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semi-conducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using a local interconnect.
The local interconnect is typically a relatively low-resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as a via or trench that connects the selected regions together. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit's performance. Accordingly, as the densities of the circuits increase there is a continuing need for more efficient, effective and precise processes for forming smaller local interconnects.
One critical factor in the fabrication of local interconnects is the alignment of the local interconnect with respect to other regions or areas of the semiconductor device(s). It is important to keep the local interconnect electrically isolated from those regions or areas that are not to be electrically connected via the local interconnect. For example, if a local interconnect is to be provided only to a drain region of a transistor arrangement, the local interconnect should be aligned such that the local interconnect does not electrically contact the transistor's gate conductor and/or source region. Controlling the alignment of the local interconnects during damascene formation can be challenging and the difficulty in doing so is increased as the critical dimensions of the device shrinks. Given the very small areas and regions in sub-quarter micron devices, the tolerance for proper alignment of the local interconnecting trenches or vias (i.e., etched openings) is extremely small. If a local interconnect is misaligned and accidentally contacts another area or region, then the device may fail to operate as required.
Thus, there is a continuing need for improved methods and arrangements for forming local interconnects, and in particular to prevent the local interconnects from electrically contacting the wrong areas or regions due to misalignment.
SUMMARY OF THE INVENTION
The present invention provides improved methods and arrangements for forming local interconnects, and in particular that provide an additional insulating layer within the semiconductor device arrangement that prevents the local interconnect from electrically contacting the gate conductor due to alignment errors.
The above stated needs are met by a semiconductor device arrangement, in accordance with one aspect of the present invention, which includes a substrate, a gate arrangement, an insulating layer and at least one local interconnect. In accordance with one embodiment of the present invention, the substrate includes a source region and a drain region each of which are formed within an active region area. The gate arrangement is formed on the substrate and extends over the active region area and above and between the source and drain regions. The gate arrangement includes a gate conductor having an exposed top surface. The insulating layer covers at least a portion of the gate arrangement that is located above the active region area and at least a portion of the exposed top surface of the gate conductor. The local interconnect is formed above the active region area and electrically contacts a contact portion of the substrate within the active region are In this unique arrangement, the local interconnect is electrically isolated from the gate conductor by the insulating layer. Thus, for example, a misaligned local interconnect is electrically insulated from the gate arrangement by the insulating layer.
The above stated needs are also met by a method for forming a local interconnect in a semiconductor device, in accordance with yet another aspect of the present invention. In one embodiment of the present invention, the method includes forming a gate conductor on a substrate, depositing a first dielectric layer over at least a first area of the gate conductor, and depositing a second dielectric layer over at least a portion of the first dielectric layer. The first and second dielectric layers are preferably made of different materials. The method includes selectively patterning the first and second dielectric layers by removing a portion of the second dielectric layer to expose a portion of the underlying first dielectric layer, and removing the exposed portions of the first dielectric layer such that the remaining patterned portions of the first and second dielectric layers are covering at least a portion of the first area of the gate conductor. The method includes depositing a third dielectric layer over the remaining patterned portion of the second dielectric layer and at least a portion of the substrate, and forming a fourth dielectric layer over the third dielectric layer. The third and fourth dielectric layers are preferably made of different materials. The method further includes forming at least one etched opening by selectively removing a portion of the fourth dielectric layer to expose a portion of the underlying third dielectric layer, and removing a portion of the third-dielectric layer to expose a portion of the underlying substrate. As a result, the etched opening can be filled with at least one conductive material, such that the gate conductor and the conductive material are electrically isolated by at least a portion of the first dielectric layer.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
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Chan Darin A.
En William G.
Foote David K.
Ngo Minh Van
Wang Fei
Advanced Micro Devices , Inc.
Lebentritt Michael S.
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