Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-11
2002-12-10
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S350000, C257S352000, C257S353000, C257S355000, C257S374000, C257S375000, C257S376000
Reexamination Certificate
active
06492684
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a silicon-on-insulator (SOI) chip and, more particularly, to an SOI chip having an isolation barrier to prevent the diffusion of impurities into active regions of the chip.
BACKGROUND
As the scale of integration increases in the manufacture of integrated circuits, devices become smaller and more sensitive to impurities. During the packaging of a semiconductor chip, impurities from the packaging environment can enter the chip, diffuse into silicon junctions, and compromise the reliability and performance of the integrated circuit. Semiconductor manufacturers have known this for some time and invest in manufacturing equipment to minimize the introduction of impurities during integrated circuit manufacturing.
Typical impurities include mobile ions such as Na, Fe, or other diffusing species. One conventional process of providing a barrier preventing these impurities from entering the chip includes coating the chip with a passivation layer around the outside and top of the chip. Typical materials used as a passivation layer include silicon nitride or metal levels formed during the chip wiring. Such a barrier works for conventional semiconductor chips which do not have a buried oxide layer (or BOX).
A BOX is endemic to the silicon-on-insulator (SOI) chip structure and represents a path for the migration of impurities if exposed. Indeed, this path is laid open to just such exposure when the individual chips are diced from the wafer before packaging. A conventional SOI chip
1
, illustrated in
FIG. 1
, includes a silicon substrate
10
and an oxide layer
12
deposited above substrate
10
. A silicon layer
14
is deposited above oxide layer
12
. Silicon layer
14
includes at least one shallow trench
34
extending through silicon layer
14
to electrically separate active regions within silicon layer
14
from one another. These active regions typically include transistors formed in silicon layer
14
. Trenches
34
are typically filled with an insulative oxide material.
A gate
18
is deposited above silicon layer
14
. A passivation layer
26
is deposited above silicon layer
14
and around gate
18
. A barrier material
20
is deposited above passivation layer
26
. Barrier material
20
is typically a dielectric material such as phosphosilicate glass (PSG), BPSG, nitride, or other similar material. Gate metal contact
30
is deposited above gate
18
, as illustrated in
FIG. 1
, such that gate metal contact
30
extends from the top of SOI chip
1
through barrier material
20
and passivation layer
26
to form an electrical contact with gate
18
. Second and third metal contacts
40
are then deposited above silicon layer
14
, as illustrated in
FIG. 1
, such that metal contacts
40
extend from the top of SOI chip
1
through barrier material
20
and passivation layer
26
to form electrical contacts with selected areas of silicon layer
14
.
Unlike other types of semiconductor chips, an SOI chip
1
is not adequately protected from impurities by merely coating the outside and top of the SOI chip
1
with a passivation layer
26
. This is because SOI chips
1
are manufactured by dicing, which causes SOI chips
1
to have diced edges, such that edges
42
of oxide layer
12
buried within the SOI chip
1
are exposed to the outside environment. The exposed edges
42
act as an entryway for impurities notwithstanding coating of the outside and top of the SOI chip
1
with a passivation layer
26
. Once inside oxide layer
12
, the impurities may diffuse into various regions of the SOI chip
1
.
The SOI chip
1
is particularly sensitive to contamination from these impurities after chip dicing but before packaging. Contamination at this particular juncture of the manufacturing process can result in loss of manufacturing yield. Accordingly, there is a need for an additional barrier to impurities diffusing into the SOI chip
1
from along the edges
42
of oxide layer
12
.
A process of passivating SOI chips
1
to prevent contamination by mobile ions before chip packaging has been described by K. Motonori in Japanese Published Patent Document No. 6-177242. Montonori describes a device in which an ion diffusion barrier is deposited alongside a silicon-buried oxide layer to protect this layer from mobile ion contamination. This device, although it protects the exposed edges of the chip and may fulfill the desired function, has several significant drawbacks.
The process of exposing the edges of SOI chips before dicing involves several potentially defect-producing steps which may reduce the overall manufacturing yield of the integrated circuits. First, the process described by Motonori, for passivating the edges of the SOI integrated circuits, requires two photolithography steps and two etching steps involving reactive ion etching. The etching steps consist of etching through many insulator films, a total thickness of well over 10,000 angstroms, and exposing the completed integrated circuit to charging damage due to the long duration of the reactive ion etching plasma steps.
Second, Motonori describes a process by which the diffusion barrier is removed from the chip dicing area just before dicing, which requires a second photolithography step and alignment to the regions to be removed. The addition of this step increases the size of the dicing region, leaving less area on each wafer for integrated circuits. This leads to larger “footprint” or die sizes. Larger die sizes often decrease the amount of chips available per wafer, causing manufacturing cost to increase.
Finally, the conformality, or ability to deposit a uniform film of the ion diffusion barrier on a vertical surface over 10,000 angstroms deep, is critical to the effectiveness of the barrier. Any break in the film would risk contamination of the final chip by mobile ions.
To overcome the shortcomings of conventional SOI chips, a new SOI chip is provided. An object of the present invention is to provide a mobile ion barrier between the edges of the exposed SOI integrated circuit and the integrated circuits within the exposed SOI integrated circuit. A related object is to provide an integrated diffusion barrier within the SOI chip itself, having a shallow depth, minimal lateral dimensions, and a planar surface. It is another object of the invention to provide an isolation groove structure as the integrated diffusion barrier and to fill the isolation groove with films that are part of the existing semiconductor fabrication sequence. It is a further object of the invention to provide an integrated diffusion barrier, within the integrated circuit area, which does not require additional area in the dicing channels for either a barrier layer or any photolithography steps which would increase the size of the integrated circuit area.
To also overcome the shortcomings of conventional processes of manufacturing SOI chips, a new process of manufacture is provided. An object of the present invention is to reduce processing steps. A related object is to manufacture an integrated diffusion barrier using a single photolithography mask and a single reactive ion step. Another object is to subject the integrated circuit to less charging due to reduced exposure to reactive ion etching.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides an SOI chip including a substrate, a buried oxide layer deposited above the substrate, and a silicon layer deposited above the oxide layer. A gate oxide layer is deposited above the silicon layer. A gate is deposited above the gate oxide layer. A gate metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The SOI chip has an isolation barrier extending through the silicon layer and the buried oxide layer to prevent diffusion of impurities into the buried oxide layer. The isolation barrier surrounds the gate, the first metal contact, the second
Bolam Ronald J.
Kulkarni Subhash B.
Schepis Dominic J.
Abate Joseph P.
Abraham Fetsum
Ratner & Prestia
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