Method of fabricating a trenched flash memory cell

Details Method of fabricating a trenched flash memory cell Method of fabricating a trenched flash memory cell

2001-02-09

2002-08-20

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000, C438S250000, C438S255000, C438S265000, C438S270000, C438S280000, C438S315000

Reexamination Certificate

active

06436765

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a trenched flash memory cell, and more particularly, to a method of fabricating a trenched flash memory cell to raise the coupling ratio (CR) and hence improve the electrical performance of the element.
2. Description of the Prior Art
A stacked-gate flash memory cell comprises a floating gate for storing electric charges, a controlling gate for controlling the charging of the floating gate, and an ONO (oxide-nitride-oxide) dielectric layer positioned between the floating gate and the controlling gate. Similar to a capacitor, the flash memory stores electric charges in the floating gate to represent a digital data bit of “1”, and removes charge from the floating gate to represent a digital data bit of “0”.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional diagram of a conventional stacked-gate flash memory cell
10
. As shown in
FIG. 1
, the flash memory cell
10
comprises a stacked gate
14
positioned on the surface of a silicon substrate
12
, a source
24
and drain
26
positioned adjacent to each side of the stacked gate
14
. The stacked gate
14
is composed of a tunnel oxide layer
16
, a floating gate
18
, an ONO dielectric layer
20
and a controlling gate
22
, respectively. By virtue of channel hot electrons (CHE) effects, the hot electrons are injected into the floating gate
18
from the drain
26
through the tunnel oxide layer
16
so as to achieve data storage. A Fowler Nordheim tunneling technique is used for data erase, which involves grounding of the controlling gate
22
or applying a negative voltage to the controlling gate
22
. As a result, the drain
26
is highly biased so as to expel the electrons trapped in the floating gate
18
.
In general, a coupling ratio (CR value) is used as an index to evaluate the performance of a flash memory cell. Assuming that C
1
is the capacitance between the floating gate
18
and the controlling gate
22
, C
2
is the capacitance between the floating gate
18
and the source
24
, C
3
is the capacitance between the floating gate
18
and the silicon substrate
12
, and C
4
is the capacitance between the floating gate
18
and the drain
26
, the CR value of the flash memory cell
10
is defined as:
CR=C
1
/(
C
1
+C
2
+C
3
+C
4
)
Wherein, the higher the coupling ratio, the better the performance of the flash memory cell. According to the above equation, one method of increasing the CR value is to increase the capacitor surface between the floating gate
18
and the controlling gate
22
, as this surface is proportional to the capacitance C
1
. However, surface enlargement is limited as the line width of either the floating gate
18
or the controlling gate
22
is defined to increase the element integration. Thus, difficulty occurs in raising both the capacitance and accessing speed of the flash memory cell
10
through the increase of the surface area of the floating gate
18
or the controlling gate
22
. In addition, although the stacked-gate flash memory cell
10
enhances integration, it is, however, prone to over-erasing.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of fabricating a trenched flash memory cell to efficiently increase the CR value and simultaneously improve the electrical performance of the elements.
In a preferred embodiment of the present invention, a plurality of shallow trench isolation (STI) structures are formed to enclose at least an active area in a silicon substrate. Next, a first ion implantation process is performed on the silicon substrate to form a doped region, followed by the deposition of an isolation layer on the surface of the silicon substrate. A first photo and etching process (PEP) is performed to form two trenches within the active area. A tunnel oxide layer, a floating gate, and an ONO dielectric layer are then formed, respectively, on the inner surface of the trenches. Subsequently, a doped polysilicon layer is formed on the silicon substrate to fill the trenches. A second PEP is performed to remove a portion of the doped polysilicon layer so as to form two controlling gates in the active area. A self-alignment source (SAS) etching process is then performed to form a common source between the two controlling gates. A plurality of spacers are then formed on the either side of each controlling gate. At last, a self-alignment silicide (salicide) process is performed to form a silicide layer on the surfaces of both the controlling gates and the common source to finish the fabrication of the trenched flash memory cell of the present invention.
It is an advantage of the present invention that the trench structure buried in the silicon substrate is used to form the stacked gate of the stacked-gate flash memory cell. The coupling surface area between the floating gate and the controlling gate is thus efficiently increased by increasing the depth or width of the stacked gate buried within the silicon substrate. As a result, integration of the elements formed thereafter on the silicon substrate is not sacrificed, and the accessing speed of the flash memory cell is raised.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


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