Dual-RIE structure for via/line interconnections

Details Dual-RIE structure for via/line interconnections Dual-RIE structure for via/line interconnections

1999-05-26

2002-08-13

Clark, Jhihan B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S773000, C257S751000, C257S758000

Reexamination Certificate

active

06433436

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an on-chip interconnect structure and to a method of fabricating the inventive on-chip interconnect structure for use in semiconductor/display technology.
BACKGROUND OF THE INVENTION
As the number of transistors and functions on a CPU chip increases, there exists a need for interconnecting such devices with minimum delay and high wiring yield. This point is illustrated in the Semiconductor Industry Association (SIA) roadmap.
In recent years, there has been a rapid development in back-end-of-the line (BEOL) wiring technology used in fabricating semiconductor chips. Presently, VLSI circuits use Al—Cu for via/interconnects. Such a structure, which is shown in
FIGS. 1
a
-
1
b
, is mainly used in logic and memory applications. In such structures, an Al—Cu layer is conventionally used as an interconnect region which is in contact with a via filled with chemical vapor deposited (CVD) tungsten (W). Once the front end devices are formed, W is filled in the contact holes and short interconnect lines
105
, i.e. the M0 or low resistivity interconnect lines, are formed using a liner/diffusion barrier. After W is polished off from the field area to form M0 interconnect and contacts, an oxide or other dielectric material
100
is deposited on top of the M0/contact structure, and via holes
90
are patterned and etched into oxide
100
to contact down to M0 level
105
(See,
FIG. 1
a
).
As shown in
FIG. 1
b
, CVD W
106
is formed in the via which is lined with a liner/barrier
104
and thereafter the CVD W is polished off from the field area. Liner
102
is formed on the structure and a low resistivity interconnect line
103
composed of Al—Cu is deposited on the planar surface by sputtering. Another liner/barrier layer
102
is formed on top of interconnect line
103
and then layers
102
and
103
are patterned using conventional lithography and reactive-ion etching (RIE). This method provides the patterned structure shown in
FIG. 1
b
. It is noted that in this structure interconnect regions
105
and
103
are isolated from CVD W
106
by liner/barrier regions
104
and
102
.
The structure illustrated by
FIGS. 1
a
-
1
b
causes electromigration problems due to inhomogeneous interfaces which are formed by flux divergence. Since CVD W has a high melting point, it does not move under an electron current. Al—Cu, on the other hand, does move under an electron current thereby creating a void at the interface of CVD W
106
and interconnect regions
105
and
103
.
To avoid this problem, interconnect region
103
is deposited into vias as well as on the planar surface as shown in
FIGS. 2
a
-
2
b
and then etched to form the via and line in one step. This particular prior art method has drawbacks associated therewith which include: (1) the need for depositing Al—Cu at high temperatures (above 400° C.) to fill the vias; (2) improved liners which cause inhomogeneous interfaces that lead to electromigration problems; and (3) the repetition of high temperature deposition to form multilevel interconnects which can cause stress voiding especially on already formed layers.
Alternate methods of using Al—Cu, Cu, or Cu-alloys as interconnects are also known in the prior art. One prior art method is a dual damascene structure shown in
FIGS. 3
a
-
3
b
wherein a thick oxide/thin nitride mask is first deposited. Using lithography and RIE, lines are patterned by removing the thin nitride mask. Via holes are then printed on the resist and the lines/vias are etched to the desired depth by RIE. The lines/vias are filled with a suitable metal using a physical vapor deposited (PVD) liner
107
and metal seed layer, and then interconnect
103
is formed by CVD or electroplating. Any metal on the field is polished off to form an interconnect and via in one step. Prior art dual damascene techniques require good metal fill characteristics. When Al—Cu is employed in prior art damascene processes, such techniques require high temperatures, wherein any subsequent polishing step becomes a problem; polishing adds one more expensive steps in the integration of these metals.
As integration continues on Ultra Large Scale the cost of wafer manufacturing increases significantly. Conventional low cost DRAM (dynamic random access memory) based technologies and DSP processors still use Al—Cu interconnect and additional polishing steps to form lines/vias which can increase the cost of fabrication. The prior art method shown in
FIGS. 2
a
-
2
b
, which relies on homogeneous interfaces, requires high temperature deposition and multistep processing (especially deposition by CVD followed by high temperature PVD deposition). The alternative prior art method, which is shown in
FIGS. 3
a
-
3
b
, relies on polishing to form interconnect lines. The polishing step is challenging due to scratching, erosion and pattern sensitivity problems (i.e. large areas get eroded faster and smaller less). For DRAM applications, polishing of Al—Cu interconnects adds to the overall processing cost. As the dimensions get very fine, particularly for Cu metallurgy, the liner thickness consumes the large area in a dual damascene process. This can lead to increased resistivity.
Based on the above drawbacks with prior art processes, there exists a need for developing a new and improved method and structure which is capable of forming an interconnect line and via in one step or multisteps. Any method developed should be applicable to both logic and memory devices as well as system-on-chip applications. It would be especially beneficial if a method was developed which could form the via in the structure prior to line fabrication. Such a method would maintain the interfacial integrity between the via and line regions resulting in high electromigration performance.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a semiconductor structure wherein a via and an interconnect line (sometimes referred to herein as metal line or wire) are made sequentially in one step, rather than prior art multistep processes.
Another object of the present invention is to provide a method of fabricating a via/interconnect structure which has high electromigration performance associated therewith due to interfacial integrity that exists between the vias and lines of the structure.
A further object of the present invention relates to a method of fabricating a via/interconnect structure wherein the interconnect lines do not encounter any polishing steps during the manufacture thereof.
A still further object of the present invention is provide a method of fabricating a via/interconnect structure wherein CVD W is employed as the via fill material and Al—Cu is employed as the metal line or interconnect material.
A yet further object of the present invention is to provide a multistep process wherein two RIE steps are employed in forming metal lines and vias. In the multistep process, no polishing step is utilized in fabricating the interconnect structure.
These and other objects and advantages are achieved utilizing the methods of the present invention. In one method of the present invention, a via is first defined and thereafter the metal line is formed. In another method of the present invention, two RIE steps are used in forming the metal lines and vias of the interconnect structure.
Specifically, the first method of the present invention comprises the steps of:
(a) forming a metal stack on a surface of a substrate, said metal stack comprising deposition of at least a first metal layer and a second metal layer;
(b) forming a masking layer on said metal stack provided in step (a);
(c) patterning said masking layer providing a via mask on said metal stack;
(d) etching said metal stack using said via mask to first define vias in said metal stack and thereafter metal lines, said vias being composed of said second metal layer and said metal lines being composed of said first metal layer;
(e) depositing a dielectric material on said structure provided in step (d) surrounding said via

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