Shallow-implant elevated source/drain doping from a sidewall...

Details Shallow-implant elevated source/drain doping from a sidewall... Shallow-implant elevated source/drain doping from a sidewall...

1999-06-17

2002-02-12

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S301000, C438S304000

Reexamination Certificate

active

06346447

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and specifically to doping of elevated source/drain structures having a shallow implant.
Background: Elevated Source/Drain Junctions
As CMOS is scaled to deep submicron regime (i.e., tenth-micron and below), MOSFETs need to have low source/drain resistance, low source/drain junction depth, and (importantly) low junction capacitance. Elevated source/drain (S/D) junction MOSFETs have been found useful in eliminating short channel and hot-carrier behavior in deep submicron CMOS technologies. See e.g., J. R. Pfiester et al., “Reverse Elevated Source/Drain (RESD) MOSFET for Deep Submicron CMOS,” IEDM 885 (1992), which is hereby incorporated by reference. In this approach, silicon.deposited by selective epitaxy forms islands of silicon crystals on a silicon substrate to extend source/drain regions upward. This upwardly extended region will be referred to as an elevated source/drain. However, not all of this region functions electrically as a source/drain because the entire raised region is not all doped with the source/drain's conductivity type.
Processes using selective epitaxial deposition for the engineering of elevated source/drain regions have performance problems which are related to, among other things, facet formation. Faceting is caused by the anisotropy of the selective epitaxial deposition process. Therefore, depending on orientation of the specific device in relation to the crystal axes of the wafer, faceting may or may not occur. For example, orientation
606
shown in
FIG. 5
results in facet formation during the selective epitaxial deposition process. Faceting causes a thinning of the epitaxial silicon near the field dielectric and gate edges.
Dual sidewall spacers have been proposed to prevent some of the problems caused by faceted regions. See e.g., Mark Rodder, “Raised Source/Drain MOSFET with Dual Sidewall Spacers,” 12
IEEE Electron Device Letters
89 (1991), which is hereby incorporated by reference.
FIG. 6A
shows a previously disclosed elevated source/drain MOSFET with dual sidewall spacers
240
′ and
260
′. First spacer
240
′ was formed, then LDD n− (or p− for PMOS) regions
214
were implanted. Elevated source/drain regions
250
′ were formed next by selective epitaxial silicon deposition. Second spacer
260
′ was then formed to overlie any faceted regions of the epitaxial silicon
250
′ near the gate edge. High-dose n+ (or p+) implants were then performed into elevated source/drain regions
250
′ to form source/drain doped regions
216
. Because second spacer
260
′ overlies any faceted regions of the epitaxial silicon
250
′, source/drain dopants are prevented from being implanted through these faceted regions, which would otherwise result in a deeper than desired junction depth. This method, however, does not provide low junction capacitance in addition to low source/drain resistance and shallow junction depth.
Attempts have been made to avoid these problems by controlling the facet angle. See e.g., Mazure et al., “Facet Engineered Elevated Source/Drain by Selective Si Epitaxy for 0.35 Micron MOSFETs”, IEDM, 853 (1992), which is hereby incorporated by reference. However, this method is dependent on controlling the angle of the facet formed, thus imposing additional requirements on process control which may not be easy to meet.
Nonfaceted transistors may also pose a problem. In particular, elevated source/drain regions of nonfaceted transistors have vertical sidewalls. These vertical sidewalls will not be doped by a shallow implant. Thus, if the epitaxial material is undoped and a shallow N+implant is used (as is desirable to minimize capacitance), a gap will exist between the implanted N+part of the elevated source/drain and the channel region. This gap makes the transistor inoperable, or at least decreases drive capability.
Background: Shallow Junctions from Doped Sidewall Spacers
Shallow junctions have previously been designed for study in an experimental structure. The shallow junctions were formed by a technique of solid-phase diffusion from sidewall spacers of phosphorous-doped (or boron-doped) silicated glass. See Ono et al., “Sub-50 nm Gate Length N-MOSFETS with 10 nm Phosphorous Source and Drain Junctions,” IEDM 119 (1993), which is hereby incorporated by reference. In this experimental technique illustrated in
FIG. 6B
, a 40 nm gate length polysilicon gate
130
was formed on 3 nm thick gate insulator
120
, which was formed on substrate
100
. PSG (or BSG) sidewalls
140
were formed to be 190 nm thick, and then used as a mask, along with gate
130
, to implant deep source/drain regions
150
into substrate
100
. A rapid thermal anneal followed, which caused the phosphorous (or boron) to diffuse into substrate
100
, forming shallow junctions (10 nm)
160
next to deep source/drain regions
150
in substrate
100
.
Elevated Shallow-Implanted Source/Drain with Additional Doping from a Sidewall Dopant Source
The present application discloses a facet-angle-independent process to provide low junction capacitance, low source/drain (S/D) resistance and shallow junction depth for both faceted and non-faceted transistors. The disclosed method uses sidewall spacers as a solid dopant source. Dopants from the sidewall spacers outdiffuse upon annealing to form a doped extension from the doped regions of the elevated source/drain, along the edge of source/drain regions, to underneath the gate electrode. This doped extension creates a path between the shallow implanted region of the elevated source/drain and the channel region.
Low junction capacitance is achieved because the shallow implant of the elevated source/drain regions places the junction inside the source/drain region itself. Low source/drain resistance is achieved because the additional diffused doped region provides a doped path from source/drain regions to the channel region. In a sample embodiment, low source/drain junction depth is achieved because a second spacer prevents dopant from being implanted into the substrate through any faceted areas. Furthermore, the doped extensions of the source/drain regions have exceptionally low junction depth. A shallow implant of source/drain regions avoids dopant segregation to implant damaged regions because areas at the edge of the channel region are less likely to be damaged by a shallow implant. The overall process is simpler because it is not facet angle dependent.


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