Semiconductor device with impedance controllable output buffer

Details Semiconductor device with impedance controllable output buffer Semiconductor device with impedance controllable output buffer

2001-09-14

2002-10-15

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189080, C326S027000, C326S026000, C326S030000, C326S086000, C326S087000

Reexamination Certificate

active

06466487

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 USC 119 to Japanese Patent Application No. P2000-282482 filed on Sep. 18, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with an output buffer for providing data to an output terminal such as an I/O pad. In particular, the present invention relates to a semiconductor device such as a memory with an output buffer whose impedance is controllable to external impedance.
2. Description of the Related Art
MPUs (microprocessor units) are increasing their performance to require high-speed memories. Some memories such as external cache memories must operate at several hundred megahertz. When transferring data from a memory to an MPU at such high speed, signal reflection that impairs signal transmission occurs in a data bus on a board where the MPU and memory are installed. To avoid such impairment, the impedance of an output buffer of the memory must be equalized with the impedance of the data bus. The faster a semiconductor device operates, the higher the accuracy of impedance control is required for the semiconductor device. There is a need of controlling the impedance of an output buffer, to correct various impedance deviations occurring on the output buffer.
Manufacturing variations and operating conditions such as temperatures and voltages of a semiconductor device cause the driving characteristics of output buffer transistors of the semiconductor device to deviate from designed characteristics. To correct the deviations and adjust the driving characteristics of the output buffer transistors to the designed ones by changing impedance of the output buffer circuitally, the semiconductor device must have a programmable impedance control function.
FIG. 1
shows an example of a circuit realizing the programmable impedance control function according to a prior art. This circuit is disclosed in ISSCC 96 FA 9.3 “A 300 MHz, 3.3 V 1 Mb SRAM Fabricated in a 0.5 &mgr;m CMOS Process.” In
FIG. 1
, an output buffer
111
has pull-up NMOS transistors
1
Y,
2
Y,
4
Y, and
8
Y and pull-down NMOS transistors
1
Z,
2
Z,
4
Z, and
8
Z. An evaluator
112
has a dummy buffer having transistors
1
X,
2
X,
3
X, and
4
X corresponding to the transistors
1
Y to
8
Y and
1
Z to
8
Z. In the evaluator
112
, a terminal VQ is connected to an external resistor RQ. The resistor RQ has resistance equal to or a multiple of the impedance of a bus which is an impedance control target. An NMOS transistor
112
a
and resistors R
0
and R
1
form a reference current source to generate two voltages VZQ and VEVAL, which are compared with each other in a voltage comparator
113
. The comparator
113
provides a comparison result to an U/D (up/down) counter
114
. The counter
114
equalizes the voltages VZQ and VEVAL with each other by turning on and off the transistors
1
X to
4
X of the dummy buffer. Namely, the impedance of the dummy buffer is adjusted to the impedance of the external resistor RQ.
Data pieces A
0
to A
3
used to control the transistors
1
X to
4
X are transferred to the output buffer
111
through an update controller
119
, to selectively turn on and off the transistors
1
Y to
8
Y and
1
Z to
8
Z. As a result, the impedance of the output buffer
111
is equalized with the impedance determined by the external resistor RQ.
The pull-up transistors
1
Y to
8
Y and pull-down transistors
1
Z to
8
Z in the output buffer
111
are NMOS transistors, and therefore, involve an equal deviation from a designed value. It is possible, therefore, to adjust the impedance of these pull-up and pull-down transistors with the single-system dummy buffer of the NMOS transistors
1
X to
4
X.
There is also an output buffer composed of pull-up PMOS transistors and pull-down NMOS transistors. For this type of output buffer, it is necessary to prepare a dummy buffer of NMOS transistors and a dummy buffer of PMOS transistors, to separately control the impedance of the pull-up and pull-down sides of the output buffer. Such separate impedance control is necessary because the PMOS transistors involve driving characteristic deviations that are different from those of the NMOS transistors.
FIG. 2
shows an example of an output buffer employing two dummy buffers to separately control the impedance of pull-up and pull-down transistors according to another prior art. The pull-up transistors in the output buffer are PMOS transistors, and the pull-down transistors therein are NMOS transistors. This output buffer is prepared for a semiconductor device that is driven by standard source voltages VDD and VSS. The output buffer is connected to an I/O pad or an output terminal
20
whose high and low levels are determined based on source voltages VDDQ and VSSQ. The voltage VDDQ is applied to the sources of the pull-up PMOS transistors
2
a
-
11
to
2
a
-
15
, and the voltage VSSQ is applied to the sources of the pull-down NMOS transistors
2
b
-
11
to
2
b
-
15
. Here, VSSQ=VSS (=0 V), and VDDQ<VDD. These conditions are applied through the following explanation.
The gates of the NMOS transistors
2
b
-
11
to
2
b
-
15
and PMOS transistors
2
a
-
11
to
2
a
-
15
receive the outputs of CMOS circuits
2
b
-
6
to
2
b
-
10
and
2
a
-
6
to
2
a
-
10
, respectively. The outputs of these CMOS circuits are logical results of read data Dout, output enable signals OE and /OE, and control signals UN and UM for controlling the impedance of the output buffer. In response to the outputs of the CMOS circuits, the PMOS transistors
2
a
-
11
to
2
a
-
15
and NMOS transistors
2
b
-
11
to
2
b
-
15
are turned on and off.
The gates of the NMOS transistors
2
b
-
11
to
2
b
-
15
receive VDD as a high level voltage and VSS as a low level voltage. The reason why the voltage VSS is applied as a low level voltage to the gates of the NMOS transistors
2
b
-
11
to
2
b
-
15
is because VSSQ=VSS, and therefore, VSS is needed to turn off the NMOS transistors
2
b
-
11
to
2
b
-
15
. The reason why VDD is applied as a high level voltage to the gates of the NMOS transistors
2
b
-
11
to
2
b
-
15
is because the CMOS circuits
2
b
-
6
to
2
b
-
10
connected to these NMOS transistors are also driven by VDD, and therefore, it is natural to employ VDD for the NMOS transistors. In addition, a higher gate voltage is preferred to increase the current driving ability of the NMOS transistors
2
b
-
11
to
2
b
-
15
, and therefore, VDD that is higher than VDDQ is applied as a high level voltage to the gates of the NMOS transistors
2
b
-
11
to
2
b
-
15
.
The prior arts mentioned above have problems. Impedance deviations to be corrected by the programmable impedance control function are caused by manufacturing variations and operating conditions including temperatures and voltages. To correct these deviations, an impedance correction range is set for each output buffer having the programmable impedance control function.
When all transistors
2
a
-
11
to
2
a
-
15
and
2
b
-
11
to
2
b
-
15
are ON in the output buffer of
FIG. 2
, the impedance of the output buffer is minimum, and when all of them are OFF, the impedance is maximum. An impedance range between these maximum and minimum impedance values shifts when currents passing through the transistors
2
a
-
11
to
2
a
-
15
and
2
b
-
11
to
2
b
-
15
change due to manufacturing variations or operating conditions. If the currents passing through the transistors decrease, the impedance range shifts to a higher side as shown in
FIG. 3A
, and if the currents increase, the impedance range shifts to a lower side as shown in FIG.
3
B.
If the impedance range of the output buffer of
FIG. 2
is between 35 &OHgr; and 70 &OHgr;, the transistors
2
a
-
11
to
2
a
-
15
and
2
b
-
11
to
2
b
-
15
must cover the range of 35 &OHgr; to 70 &OHgr; irrespective of manufacturing variations or operating conditions. Namely, an overlapping part of
FIGS.

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