Method of forming conducting diffusion barriers

Details Method of forming conducting diffusion barriers Method of forming conducting diffusion barriers

2000-03-16

2002-06-25

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S627000, C438S643000, C438S648000, C438S653000, C438S656000, C438S659000, C438S695000, C438S687000

Reexamination Certificate

active

06410383

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor technology and more particularly to a method of forming conducting diffusion barriers for semiconductor devices.
Diffusion barriers are commonly used in integrated circuit (IC) fabrication to prevent interdiffusion of metals. For example, a TiN film is used to prevent diffusion of Al into Si at contact regions and along metal lines. As the dimensions of ICs, particularly contact regions and metal lines, continue to shrink, the requirements for the conducting barrier also become more stringent. Thinner barriers are required without substantially increasing resistivity. Barriers also need to be more resistant to diffusion of various new metals, which are being introduced into production processes. One of the metals that is being introduced is copper. Although few diffusion barriers materials effectively block the diffusion of copper, metal nitride and silicon nitride have been shown to act as good barriers against copper diffusion. However, thin films with desired composition and conductivity cannot be easily deposited. This is especially true for ternary or quaternary materials.
ICs typically have structures at different heights. These structures form steps. Many of the materials being investigated for use as diffusion barriers, do not have good step coverage when deposited using conventional means. For instance, conventional sputtering methods suffer from problems of poor step coverage and composition control, especially for ternary or quaternary materials.
Step coverage refers to the ability of a deposited material to follow the underlying step to provide desirable coverage. Step coverage is defined in terms of the ratio of the thickness of the thinnest region, which is typically at the bottom corners, versus the thickness of the material deposited over a flat upper region, expressed as a percentage. Step coverage is considered good if it is equal to or greater than 70%.
Another problem associated with step coverage is caused by an over accumulation of material on the upper edges of the step. As the width of metal lines and other features get thinner, the over accumulation of material at the upper edge of a trough, also referred to as an overhang, has a tendency to significantly reduce the effective width of the feature. If the reduced effective width becomes too small, subsequent metalization processes will be unable to adequately fill the bottom of the trench.
It would be advantageous if an alternative method of forming a diffusion barrier with good step coverage and the desired characteristics could be provided.
SUMMARY OF THE INVENTION
Accordingly, a method of forming a diffusion barrier is provided. The method comprises the steps of:
a) providing a semiconductor substrate;
b) depositing a layer of an initial material; and
c) implanting ions into the initial material to form a desired material.
Following implanting, the semiconductor substrate is annealed to reduce or eliminate implant damage and achieve the appropriate composition and crystallinity. Metal is preferably deposited within a trench to form a metal line.
Preferably, the layer of initial material is formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or ion metal plasma (IMP) deposition. Deposition is preferably a low temperature deposition at less than 450 degrees Celsius. The initial material can be selected from a wide variety of materials. The initial material need not have good conductivity or barrier properties. Preferably, the initial material will provide good step coverage, and provide at least some of the material necessary to produce a final desired material having sufficient conductivity and barrier properties for the desired metal line. The initial material can comprise a single element, a binary material, or even, ternary or quaternary materials, provided they have adequate step coverage. The terms binary, ternary, and quaternary are used through out this specification to refer to materials having two elements, three elements, and four elements, respectively. In common usage, these terms refer to compounds. As used herein, these terms may include compounds, alloys or other categories of materials having the designated number of elements.
After the initial layer is deposited, ions are implanted to modify the initial material. The implanted ions should be selected such that they improve the properties of the initial material, or assist in converting the new material into a desired material. For a diffusion barrier, the implanted ions should aid in producing materials having good conductivity and barrier properties. Preferably, the ion will be implanted using plasma immersion ion implantation (PIII). The substrate will be laced within a PIII chamber. A gas containing a desired element is introduced into the PIII chamber and energized to form a plasma of ionized gas. The ions contained within the ionized gas are implanted into the silicon substrate. Preferably, the substrate will be negatively biased to attract the positive ions. Although using PIII is preferred, it is also possible to implant the ions by convention ion implantation methods or using ion metal plasma (IMP) techniques.
Following deposition and implantation, the entire semiconductor substrate is annealed to condition the implanted material. Preferably, a rapid thermal anneal (RTA) process is applied to the wafer to anneal out implant damage and to achieve the appropriate composition and crystallinity. Alternatively, a convention heat treatment is applied to the wafer using a furnace.
Subsequent processing can be performed to complete the formation of the barrier layer, including depositing a metal layer.


REFERENCES:
patent: 4920071 (1990-04-01), Thomas
patent: 5633200 (1997-05-01), Hu
patent: 5672541 (1997-09-01), Booske et al.
patent: 5882991 (1999-03-01), Paranjpe
patent: 5899740 (1999-05-01), Kwon
patent: 5953600 (1999-09-01), Gris
patent: 5966607 (1999-10-01), Chee et al.
patent: 5985759 (1999-11-01), Kim et al.
patent: 6268291 (2001-07-01), Andricacos et al.
S. Wolf, Silicon Processing for the VLSI Era, Jan. 1986, Lattice Press, vol. 1 pp. 295-296.*
Thesis by Jason S. Reid entitled, “Amorphous Ternary Diffusion Barriers for Silicon Metallizations” defended May 9, 1995.
Article entitled, “Ti-Si-N Diffusion Barriers Between Silicon and Copper”, by J.S. Reid, X. Sun, E. Kolawa and M.-A., Nicolet, published in IEEE Electron Device Letters, vol. 15, No. 8, Aug. 1994, pp. 298-300.
Article entitled, “Amorophous (Mo, Ta, or W)-Si-N Diffusion Barriers for A1 metallizations”, by J.S. Reid, E. Kolawa, C.M. Garland & M.-A. Nicolet, published in J. Appl. Phys. 79(2), Jan. 15, 1996, pp. 1109-1115.

Affiliated with

Also associated with

Rating

Method of forming conducting diffusion barriers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming conducting diffusion barriers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming conducting diffusion barriers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2945217