Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1999-04-21
2002-02-12
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S165000, C438S154000, C257S066000
Reexamination Certificate
active
06346486
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT) comprising a thin film of a non-single crystal semiconductor, and to a process for fabricating the same. The thin film transistor according to the present invention can be formed on either an insulator substrate such as a glass substrate or a semiconductor substrate such as a single crystal silicon. In particular, the present invention relates to a thin film transistor fabricated through the steps of crystallization and activation by thermal annealing.
2. Prior Art
Recently, active study is made on semiconductor devices of insulated-gate type comprising an insulator substrate having thereon a thin film active layer (which is sometimes referred to as “active region”). In particular, much effort is paid on the study of insulated-gate transistors of thin film type, i.e., the so-called thin film transistors (TFTs). The TFTs can be classified into, for example, amorphous silicon TFTs and crystalline silicon TFTs, according to the material and the state of the semiconductor employed in the TFT. The term “crystalline silicon” refers to non-single crystal silicon, which encompasses all types of crystalline silicon except single crystal silicon.
In general, semiconductors in an amorphous state have a low electric field mobility. Accordingly, they cannot be employed in TFTs intended for high speed operation. Furthermore, the electric field mobility of a P-type amorphous silicon is extremely low. This makes the fabrication of a P-channel TFT (a PMOS TFT) unfeasible. It is therefore difficult to obtain a complementary MOS (CMOS) circuit from such a P-channel TFT, because the implementation of a CMOS circuit requires combining a P-channel TFT with an N-channel TFT (NMOS TFT).
In contrast to the amorphous semiconductors, crystalline semiconductors have higher electric field mobilities, and are therefore suitable for use in TFTs designed for high speed operation. Crystalline silicon is further advantageous in that a CMOS circuit can be easily fabricated therefrom, because not only an NMOS TFT but also a PMOS TFT is available from crystalline silicon. Furthermore, it is pointed out that further improved characteristics can be obtained by establishing an LDD (lightly doped drain) structure known in the conventional single crystal semiconductor MOS ICs.
An LDD structure can be obtained by the following process steps:
forming island-like semiconductor regions and a gate insulating film;
forming a gate electrode;
introducing impurities at a low concentration by ion implantation or ion doping;
forming masks for the LDD region (by anisotropic etching of the insulating film covering the gate electrode, or by selective oxidation of the anodic oxide covering the gate electrode);
introducing impurities at high concentration by ion implantation or ion doping; and
annealing the impurities.
The most problematic in the above process is the sixth step, in which the amorphous silicon is activated by laser annealing or by thermal annealing. Laser annealing comprises irradiating a laser beam or an intense light having an intensity equivalent to that of a laser beam. However, laser annealing is not suitable for mass production, because the laser beam output is still unstable and because the beam is applied for an extremely short period of time. Furthermore, the laser beam is irradiated from the upper side of the gate electrode. It then results in an insufficiently activated LDD region, because the mask formed in the fourth step functions as a shield.
A practical process at present is thermal annealing, which comprises activating the impurities in silicon by heating. The LDD region can be sufficiently activated, and uniform batches can be realized by this process. However, in general, the impurities in the silicon film must be activated by annealing for a long period of time at about 600° C., or by annealing at a high temperature of 1,000° C. or even higher. The latter method, i.e., the high temperature annealing can be applied only to cases using quartz substrates, and the use of such expensive substrates considerably increases the production cost. The former process can be applied to a wide variety of substrates. However, the use of inexpensive substrates brings about other problems such as the shrinking of substrates during thermal annealing, because it leads to a low product yield due to the failure upon mask matching. It is therefore necessary to effect treatments at lower temperatures when such inexpensive substrates are used. More specifically, thermal treatments are preferably performed at temperatures not higher than the deformation temperature of alkali-free glass generally used in the substrates, and more preferably, at a temperature lower than the deformation temperature by 50 degrees or more.
The present invention provides a solution to the aforementioned problems difficult to solve.
SUMMARY OF THE INVENTION
As a result of an extensive study of the present inventors, it has been found that the crystallization of a substantially amorphous silicon film can be accelerated by adding a trace amount of a catalyst material. In this manner, the crystallization can be effected at a lower temperature and in a shorter duration of time. Preferred catalyst materials include pure metals, i.e., nickel (Ni), iron (Fe), cobalt (Co), and platinum (Pt), or a compound such as a silicide of an element enumerated herein. More specifically, the process according to the present invention comprises bringing the catalyst elements or a compound thereof as they are or in the form of a coating in contact with amorphous silicon, or introducing the catalyst elements into the amorphous silicon film by ion implantation and the like, and then, thermally annealing the resulting structure at a proper temperature, typically at 580° C. or lower.
Naturally, the duration of crystallization can be shortened by increasing the annealing temperature. Furthermore, the duration of crystallization becomes shorter and the crystallization temperature becomes lower with increasing concentration of nickel, iron, cobalt, or platinum. The present inventors have found, through an extensive study, that the crystallization is accelerated by incorporating at least one of the catalytic elements above at a concentration higher than 1×10
15
cm
−3
, and preferably, at a concentration of 5×10
18
cm
−3
or higher.
The catalyst materials enumerated above, however, are not favorable for silicon. Accordingly, the concentration thereof are preferably controlled to a level as low as possible. The present inventors have found through the study that the preferred range of the concentration in total is 2×10
19
cm
−3
or lower.
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Takemura Yasuhiko
Uochi Hideki
Bowers Charles
Nixon & Peabody LLP
Robinson Eric J.
Schillinger Laura M.
Semiconductor Energy Laboratory Co,. Ltd.
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