Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-12-14
2002-10-08
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S697000, C438S699000, C438S702000, C438S703000, C438S435000
Reexamination Certificate
active
06461966
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to high density plasma (HDP) pre-metal dielectric (PMD) layer deposition processes.
BACKGROUND OF THE INVENTION
The use of high density plasma (HDP) phosphosilicate glass (PSG) in the formation of pre-metal dielectric (PMD) layers raises the concerns of plasma damage. For gap-fill purposes in dealing with relatively closely spaced structures, a high bias power with low deposition: sputter (D:S) ratio is used along with a chucking bias voltage on an E-chuck (electrical chuck) for temperature control. However, the high bias power, low D:S ratio and chucking voltage all create the potential for plasma damage to the device wafer. For example, plasma damage to the structures and damage to gate oxide from the process is common.
U.S. Pat. No. 6,211,040 B1 to Liu et al. describes an HDP CVD silicon dioxide two-step deposition process to reduce plasma damage in very small feature applications. A gas mixture is used that is comprised of silane, oxygen and argon.
U.S. Pat. No. 5,968,610 to Liu et al. describes a method for depositing dielectric material into gaps between wiring lines that includes the deposition of three oxide layers using a HDP CVD.
U.S. Pat. No. 6,013,584 to M'Saad describes a process of forming a dielectric layer, such as PSG, that exhibits low moisture content, good gap fill capability, good gettering capability and compatibility with planarization techniques.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide a method of reducing HDP PSG plasma damage while achieving good gap filling.
Another object of one or more embodiments of the present invention to provide a method of increasing HDP PSG throughput while also reducing plasma damage with good gap filling.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having at least two semiconductor structures separated by a gap therebetween is provided. A first dielectric layer is formed over the structure, the two semiconductor structures and within the gap between the two semiconductor structures to a thickness as least as high as the top of the semiconductor structures by a first high density plasma (HDP) process. The first HDP process having a first high bias RF power, a low first deposition: sputter ratio and a first chucking bias voltage. A second dielectric layer is then formed over the first dielectric layer by a second HDP process to form the composite dielectric layer. The second HDP process having: a second bias RF power that is less than the first bias RF power; a second deposition: sputter ratio that is greater than the first deposition: sputter ratio; and a second chucking bias voltage that is zero.
REFERENCES:
patent: 5920792 (1999-07-01), Lin
patent: 5968610 (1999-10-01), Liu et al.
patent: 6013584 (2000-01-01), M'Saad
patent: 6211040 (2001-04-01), Liu et al.
patent: 6291030 (2001-09-01), Chao et al.
patent: 6339027 (2002-01-01), Chok
Chen Yao-Hsiang
Fu Chu-Yun
Jang Syung-Ming
Ackerman Stephen B.
Dang Trung
Saile George O.
Taiwan Semiconductor Manufacturing Company
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