Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-08-23
2002-11-26
Sherry, Michael (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C361S733000, C438S132000
Reexamination Certificate
active
06486528
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for addressing integrated circuit chips, and more particularly to a method and apparatus for addressing a stack of silicon segments.
For many years, electrical components such as transistors and integrated circuits have been made using wafers of semiconductor material, including silicon and germanium. Integrated circuits have been provided on the wafer. Individual integrated circuits that are provided on the wafer are referred to as die, and include contact points called bond pads for external electrical connections. Typically, the die on the wafer are separated from one another by cutting the wafer along boundaries defining the die. Once the die are cut from the wafer, they are referred to as chips, and are packaged for use. In recent years, the proliferation of more powerful electronic systems has led to an increased need for higher density integrated circuit packages.
One method for creating higher density packages attempts to create entire computer systems on a single wafer using wafer scale integration (WSI) techniques. WSI technology attempts to laterally wire together all the die on a wafer using wires to interconnect the die. However, in order to create the necessary interconnections between the die, many wires are required that are extremely thin and difficult to create.
A second method for creating higher density packages attempts to reduce the area required for placing the chips on a circuit board by physically stacking the chips vertically. One chip stacking technique mounts individual die on ceramic carriers, encapsulates both the die and the carrier, stacks the carriers, and then mounts the stack on a printed circuit board. In this technique, all the die in the stack are interconnected by connecting the leads of the die to the printed circuit board via metal pins. This method results in an unusually high pin count on the circuit board which reduces the reliability of the circuitry because the high pin count increases the possibility that one of the many pins may become disconnected from the board.
Another chip stacking method uses a more complex process to stack die. This method modifies individual chips by adding a pattern of metallization, called rerouting leads, to the surface of the wafer. The rerouting leads extend from bond pads on the chip to newly formed bond pads, and are arranged so that all the rerouting leads terminate on one side of the modified chip. Each modified chip is then cut from the wafer, as shown by the dotted lines, and assembled into a stack. After the leads of the chips are exposed, a layer of metallization is applied to the leads along the side of the stack in order to electrically connect each of the modified chips in the stack. The stack is then mounted and connected to a substrate which is in turn connected to conventional circuitry.
The method of rerouting leads offers improvement in circuit density over prior methods, but is complex and expensive. In addition, the rerouting leads extend over five adjacent die which are destroyed when the modified chip is cut out of the wafer. In this method, five die are sacrificed for every chip that is modified.
Another method for creating higher density circuits creates stacks from entire wafers, rather than individual chips, to form a wafer array. In some devices, the wafers in the stack are electrically interconnected using solid vertical columns of metallic conductive feed-throughs, such as copper. The use of solid feed-throughs to interconnect wafers may cause damage to the array due to differential thermal coefficients of expansion during thermal cycles. Furthermore, the process is costly and makes the wafers difficult to separate for repairs.
Other methods also exist to interconnect stacks of wafers, as disclosed in, for example, U.S. Pat. No. 4,897,708 issued Jun. 30, 1990, and U.S. Pat. No. 4,954,875 issued Sep. 4, 1990. These methods provide each wafer in the stack with coned-shaped through holes which expose bonding pads on the wafers. The bond pads of the wafers in the stack are then electrically connected by either filling the through holes with electrically conductive liquid, or inserting an electrically conductive compliant material into the through holes, to provide a continuous vertical electrical connection between the wafers. While avoiding the disadvantages of using solid vertical columns of metal to interconnect wafers, the use of electrically conductive liquids and conductive materials requires special tooling to fill the through holes. Furthermore, for some applications, it may not be desirable to use stacks of entire wafers due to size constraints of the electrical device.
In integrated circuit packages, individual chips are accessed through the use of address lines, data lines, and control lines; collectively called control lines. The address lines are divided into row and column address lines which are controlled by a row address select line and a column address select line, respectively. To electrically connect an integrated circuit package to a substrate, such as to a printed circuit board for example, the control lines are extended from individual chips in the integrated circuit packages to the circuit board via metal traces. Since the addressing of chips is, in effect, hard wired once the integrated circuit package is connected to a substrate, defective chips are typically discarded before the chips are stacked and/or connected to a circuit board in order to save space and to avoid the difficulty and expense associated with rerouting the control lines from defective chips to functioning chips.
In parent application Ser. No. 08/265,081 (now U.S. Pat. No. 5,675,180 issued Oct. 7, 1997), which is herein incorporated by reference, a vertical interconnect process (VIP) is disclosed which provides an improved method and apparatus for creating higher density packages. In VIP, a segment is formed by grouping a plurality of adjacent die on a wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects. The metal interconnects function not only to interconnect the die, but also to provide segment bond pads, which serve as external electrical connection points. After the die are interconnected, each segment is cut from the wafer so as to have beveled edge walls. Segments are then placed on top of one another to form a stack of segments, as opposed to a stack of individual chips, and the segments are electrically connected through the application of electrically conductive epoxy along the beveled edges of the stack. The stack of electrically interconnected segments is then mounted to a circuit board.
Since a portion of the die on a wafer may not function and the defective die are not cut from the wafer and discarded, addressing the stack and the die therein solely through the use of hard-wired control lines, as in prior art methods, is inadequate because a computer or the like may attempt to access a defective die in the stack.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved method and apparatus for uniquely addressing chips, as well as stacks of segments.
The present invention is a method and apparatus for programming a stack of segments that provides an addressing scheme capable of uniquely addressing each segment in a stack as well as providing access to a functioning die when an attempt is made to access a defective die in the stack. Each segment in the stack includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once segments are arranged into a stack, external circuits access the segments through control lines. Connected between all of the die on each segment and the control lines are electrically conductive fuses. The segments, which are all located on different levels of the stack, are programmed by opening the conductive fuses in a predetermined pattern on each die so that the control line associated with
Finley Michael G.
Pedersen David V.
Sautter Kenneth M.
Baldwin Stephen E.
Pert Evan
Sherry Michael
Vertical Circuits, Inc.
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