Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-08
2002-08-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000, C438S257000, C438S585000, C438S593000, C257S314000, C257S315000
Reexamination Certificate
active
06436764
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fabrication of flash memories with split gate structures, and more particularly to fabrication of flash memories utilizing nitride spacers to achieve self-alignment of the split gates.
2. Description of the Prior Art
Portable telecommunications and computing market has become a major driving force in semiconductor IC (Integrated Circuits) design and technology. The growing market requires low power, high density, and electrically re-writable non-volatile memories, either embedded or stand-alone. Flash memory is one popular choice other than EEPROM (Electrically Erasable and Programmable ROM) because of its small size and improved reliability.
Many of the existing flash memories utilize split gate structures in the memory cells. A split gate cell generally merges a select gate with a storage gate over channel region to prevent the cell from going into depletion mode as a result of overerasing. One typical flash memory with split gate cells is constructed with triple level of polysilicon (rather than two levels used in the earliest flash), as depicted in FIG.
1
. The first polysicon layer
10
formed over substrate
5
is used as both the select gate and the lower control gate. The second polysilicon
20
is a floating gate and the third poly layer
30
is the upper control gate. The floating gate is sandwiched between two layers of control gate. The capacitance between floating gate and control gate is effectively increased since the capacitance of the floating gate with the upper and lower controls gates is additive. The capacitance, however, between the floating gate and the substrate is decreased by the shielding effect of the lower control gate and select gate, therefore a low capacitance ratio is achieved resulting in a high drive current.
In order to save the cell size of flash memory, the split gate structures are often designed in symmetric shape (mirror symmetry) for junction sharing (such as junction
40
in
FIG. 1
) among the adjacent gate cells. A schematic representation of part of the cell fabrication process is shown in
FIGS. 2A
to
2
B. As shown in
FIG. 2A
, after the first conductive layer
10
having gate oxide
12
is defined and oxide layer
14
is formed to isolate the second conductive layer
20
, photo resist
24
is utilized (with optional use of a supporting isolation layer
22
) to define the second conductive layer
20
. Once the construction of the second conductive layer
20
is completed, cell junctions
40
are formed, as illustrated in
FIG. 2B
, by ion implantation.
One can noted that in the prior techniques for manufacturing the conventional flash structure, the floating gate is not self-aligned to the select gate (and the lower control gate). As a result, misalignment of the split gates often occurs during the fabrication process, and thus affects channel length of the gate cells and results in possible failing of even and odd bit lines of the circuit. For example, when an X value of lithographic misalignment takes place for the gate structures, one of the two symmetric pair cells would gain X value of channel length and another would lose X value of the length. That results in 2X value of channel length difference of the paired gates. The asymmetric channel lengths bring current variations of the adjacent gate cells. The wild current distribution could cause program mismatch and sub-threshold disturbance, which is disadvantageous for multi-level flash application.
It would be desirable to have a method for forming split gate cells using self-alignment techniques to improve product quality of the flash memories.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming split gate cells in a flash memory that substantially solves the aforementioned problems. Nitride spacer formation is used to facilitate gate etching in a self-aligning manner so that the channel length of the split gate is under proper control and the effect of misalignment can then be totally avoided.
In one embodiment, first conductive structures are first defined on a semiconductor substrate with an oxide layer forming thereon for appropriate gate isolation. Deposition of second conductive layer is then proceeded. Next, a photo resist is patterned to partially define the second conductive structures (leaving the portions that are intended to be etched by self-aligning method un-defined). After the patterned photo resist is removed, a thin oxide layer is grown on the surface of the partially defined second conductive structure as a buffer protection. Masking by the partially defined second conductive structure and the first conductive structures, implantation is performed to form several junctions within the substrate. A layer of nitride is thereafter deposited and dry etched to formed nitride spacers over side walls of the first and second conductive structures (Note: since the conductive structure surface is protected by oxide, the nitride spacers are formed in fact on the oxide surface). After the formation of the nitride spacers, conventional lithographic techniques are then applied to finish defining the second conductive structures. A thick oxide layer deposited on the second conductive structures is optionally used to facilitate the lithography process.
Due to the incorporation of the nitride spacers, the final definition of the second conductive structures can now be accomplished in a self-aligning manner. Ion implantation is then followed to complete the junction formation. The application of the self-aligning etching makes the junction formation falling in a much reliable position and thus enhances control of the channel length. The product quality of the flesh memory is therefore improved.
REFERENCES:
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patent: 6017795 (2000-01-01), Hsieh et al.
patent: 6054350 (2000-04-01), Hsieh et al.
patent: 6093945 (2000-07-01), Yang
patent: 6133098 (2000-10-01), Ogura et al.
patent: 6232180 (2001-05-01), Chen
patent: 6242309 (2001-06-01), Lee
patent: 6242774 (2001-06-01), Sung
Y. Ma. “A Novel high density contactless flash memory array . . . for 5v-only application” IEEE Symposium on VLSI Technology digest of technical papers. 1994 0-7803-19212-4/94 P. 49-50.
Lee Jr. Granvill D
Powell Goldstein Frazer & Murphy LLP
Smith Matthew
United Microelectronics Corp.
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