Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2000-03-20
2002-06-25
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
Reexamination Certificate
active
06410446
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89102402, filed Feb. 14, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of a multi-step high plasma chemical vapor deposition (HDPCVD), and more particularly to a method of filling a gap between conductive structures in a semiconductor device with dielectric material.
2. Description of the Related Art
In semiconductor devices, multilevel conductive wiring and other conductors are normally isolated by inter-metal dielectric (IMD) layers. As the dimensions of devices shrink, the aspect ratio of the gap between conductive layers is getting higher A gap with a higher aspect ratio is more difficult to fill. On the other hand, as the distance between conductive layers and other conductors becomes shorter, the capacitance increases, so that the operating speed would be affected. To achieve a higher efficiency with the shrinking dimension of devices, the dielectric layers between conductive layers are required to have characteristics such as even and uniform gap-filling, preventing water absorption, and minimizing capacitance between conductive layers by using a lower dielectric constant material.
Thus, it is important to deposit a high quality, interstice-free dielectric layer at high aspect ratio conditions. The dielectric layer is formed, for example by CVD which is performed by introducing the precursor to the deposition surface, and then, after reaction, depositing the material on the surface. Different kinds of CVD processes are in use, such as atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), and plasma enhanced CVD (PECVD). To obtain high quality oxide by APCVD and LPCVD, a higher deposition temperature such as about 650° C. to 850° C. is required. However, for some conductive material, for example, aluminum, such a high deposition temperature causes voids within the oxide. As a result, a layer containing voids is of certainly not acceptance for using at IMD layer. By PECVD, plasma provides extra energy for activating reacting gases, and therefore, the deposition is performed at a lower temperature, for example, a temperature at about 400° C. or lower.
In a conventional method of forming a dielectric layer between conductive wiring, an interlayer is formed by PECVD using silane or tetra-ethyl-ortho-silicate (TEOS) as precursor. An accompanying spin-on-glass (SOG) layer is formed on the conductive wiring and to fill the gap therebetween. However, due to its water-absorbing and interstice—forming natures, the SOG layer cannot entirely fit all the key requirements. This phenomenon is even more obvious as the devices become smaller. Thus, a method to fill the gap with a high quality dielectric material is urgently in need of development.
In addition, in a device with a smaller dimension, the conventional CVD cannot well fill in the gap at a higher aspect ratio. For example, using conventional PECVD, interstices between conductive wiring are always found due to the fact that higher arriving angle at corner given rise to a sealed at top corner. In the subsequent process, these interstices are possibly open and contaminated. Therefore, the conductive wiring or the contact is easily damaged, and the device is degraded.
FIG.
1
A and
FIG. 1B
illustrate a method of filling a gap by a conventional PECVD process. Shown in
FIG. 1A
, an oxide layer
10
is formed on a substrate
12
by PECVD with TEOS as a precursor. On an upper part of the sidewall of the conductive wiring
14
, an overhang
15
is formed. As the deposition continues, an interstice
16
is sealed as shown in FIG.
1
B. The interstice
16
is formed as a seam, lengthwise along the conductive wiring. The seam is near the end of the conductive wiring, or is restricted in the bending part of the conductive wiring. In the subsequent process, the interstice
16
is very likely to be uncovered, so that a chemical for polishing or an etching by-product is trapped by the interstice. The trapped material within the interstice is very difficult to remove, and thus, the yield of the subsequent process is degraded.
Recently, a conventional method with a high gap-filling ability for depositing dielectric material within wiring lines is high-density plasma CVD (HDPCVD). The method comprises deposition and sputtering components to obtain a good gap-filling capability. However, decreasing distance between the wiring lines when devices continually scale down, dielectric layer deposited on the wiring lines may be sputtered away due to the sputtering component of the HDPCVD process. This sputtered dielectric material would redeposit on the opposite wiring lines so that overhang is formed which degrade the gap-filling capability of HDPCVD process thereafter, as shown in FIG.
1
C. Dielectric material
17
deposited on the top of the wiring lines
14
is sputtered and redeposited from one side to another side of the wiring lines
14
.
SUMMARY OF THE INVENTION
The invention provides a method of gap filling that uses HDPCVD. The process includes different steps to control and to adjust deposition/sputtering ratio. Dielectric material can be formed within a gap without an overhang at corners of the top of the gap.
The method of the invention is applied on a substrate which has conductive structures formed thereon. A HDPCVD process is performed to form a dielectric layer on the substrate. The HDPCVD process consists of multi-steps. First, a gas source is diverted to a deposition chamber to forming dielectric material over the substrate. The gas source both comprises reactive gas and inert gas, such as argon. Thus, the first step can simultaneously have depositing and sputtering. Second, the reactive gas is driven out of the deposition chamber. Only sputtering agent from inert gas, such as argon, or from oxygen is used to remove a part of the dielectric material at top corners of the conductive structures and to redeposit the removed dielectric material on the bottom of the gap between the conductive structures. Third, the addition of the reactive gas into the deposition chamber is resumed to deposit the dielectric material until the gap is completely filled.
The multi-step HDPCVD process is performed without interruption. Bias power plasma is turned on, and the gas source flows consecutively. The reactive gas flows is diverted from a chamber for several seconds to provide an in-situ sputtering treatment on the deposited dielectric material. The supply of the reactive gas is continueously flowing into system so that time spent turning the supply on/off can be saved.
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Liu Chih-Chien
Tsai Cheng-Yuan
Yang Ming-Sheng
Anderson Matthew
United Microelectronics Corp.
Utech Benjamin L.
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