Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-14
2002-08-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000, C438S664000
Reexamination Certificate
active
06429124
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of integrated circuit design and fabrication. Specifically, the invention relates to methods for making local interconnect structures for integrated circuits and the structures formed thereby.
2. Background of Related Art
Integrated circuits (ICs) contain individual active and passive devices which are interconnected during fabrication by an intricate network of conductive material. The quality of these inter-device interconnections often affects the performance and reliability of the overall IC device.
Local interconnects, unlike other interconnects such as multi-level interconnects, electrically connect the individual devices of the overall IC device at a level or levels below customary metallization levels. For example, local interconnects connect gates and emitters to diffusion areas and N+ and P+ regions across field oxide regions. See T. Tang et al.,
Titanium Nitride Local Interconnect Technology for VLSI
, IEEE Trans. Electron Devices, Vol. ED-34, 3 (1987) p. 682, the disclosure of which is incorporated herein by reference.
Several materials have been employed in local interconnects, such as titanium nitride, refractory metals, and titanium silicide (TiSi
x
). TiSi
x
has been used frequently as a local interconnect material because of its low resistance and high conductivity. Methods for fabricating local interconnects, such as TiSi
x
local interconnects, include those described in U.S. Pat. Nos. 4,975,756, 5,589,415, 5,605,853, and 5,612,243, the disclosures of which are incorporated herein by reference.
U.S. Pat. No. 5,483,104, the disclosure of which is incorporated herein by reference, discloses a method for fabricating TiSi
x
local interconnects. Silicided regions, which protect source and drain regions from an overlying local interconnect, are formed by depositing titanium (Ti) on a silicon (Si) substrate and annealing the titanium to the silicon in a nitrogen atmosphere. The local interconnect structure is then formed on the silicide regions by depositing a doped polysilicon layer, sputtering titanium on the polysilicon, and annealing in a nitrogen atmosphere. Such a technique, however, often results in poor contact between the silicided active area and the silicided local interconnect if the polysilicon deposition is not very well controlled.
Another method for manufacturing TiSi
x
local interconnects is disclosed in U.S. Pat. No. 5,496,750 (“the '750 Patent”), the disclosure of which is incorporated herein by reference. The '750 Patent describes a method for fabricating elevated source/drain junction metal-on-silicon field effect transistors (MOSFETs) extending from gate sidewalls to isolation structures surrounding the FET gate area. Unfortunately, the method described in the '750 Patent is limited because the method disclosed therein does not include the fabrication of a flexible local interconnect structure.
Using titanium suicide as a local interconnect can result in several problems, as explained in U.S. Pat. No. 5,341,016, the disclosure of which is incorporated herein by reference. One problem is that titanium silicide severely agglomerates when exposed to temperatures greater than 850° C. Agglomeration can increase both silicided source/drain and polycide sheet resistance and lead to excessive leakage and/or gate oxide degradation. Another problem with titanium silicide is unwanted dopant segregation, which can reduce the minority carrier lifetime during device operation and cause contact resistance problems
A particular problem with TiSi
x
local interconnects has been poor step coverage. Conventionally, in forming the local interconnect, Ti has been deposited first, followed by physical vapor deposition (PVD) of silicon. PVD silicon, however, suffers from poor step coverage. This poor step coverage often detracts from the quality of the semiconductor device.
SUMMARY OF THE INVENTION
The present invention relates to a method for selectively fabricating a flexible metal silicide local interconnect over gates or other structures of a semiconductor device. The method of the present invention includes forming at least one gate structure on a substrate, disposing an amorphous or polycrystalline silicon layer on the substrate, disposing a layer of silicon nitride (SiN) over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. Preferably, the silicon layer is formed on the substrate and the at least one gate structure. In removing the portion of the silicon nitride layer, a remaining portion is preferably left overlying the at least one gate structure. More preferably, the method leaves a local interconnect layer overlying the at least one gate structure.
The present invention provides at least one advantage when compared to conventional local interconnect fabrication methods, in that the present invention forms TiSi
x
local interconnects with good step coverage because the silicon forming the interconnects is deposited via chemical vapor deposition (CVD).
Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.
REFERENCES:
patent: 4103415 (1978-08-01), Hayes
patent: 4975756 (1990-12-01), Haken et al.
patent: 5341016 (1994-08-01), Prall et al.
patent: 5360757 (1994-11-01), Lage
patent: 5483104 (1996-01-01), Godinho et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5589415 (1996-12-01), Blanchard
patent: 5605853 (1997-02-01), Yoo et al.
patent: 5612243 (1997-03-01), Verrett
patent: 5670425 (1997-09-01), Schinella et al.
patent: 2001/0009303 (2001-07-01), Tang
Thomas E. Tang et al.,Titanium Nitride Local Interconnect Technology For VLSI, IEEE Transactions On Electron Devices. vol. ED-34, No. 3. Mar. 1987.
Tang Sanh D.
Violette Michael P.
Micro)n Technology, Inc.
Niebling John F.
TraskBritt
Whitmore Stacy
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