Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-12
2002-08-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000, C438S763000
Reexamination Certificate
active
06432784
ABSTRACT:
FIELD OF THE INVENTION
The present specification relates to integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present specification relates to a method of forming L-shaped nitride spacers in an integrated circuit.
BACKGROUND OF THE INVENTION
Transistors are generally formed on the top surface of a semiconductor substrate. Typically, the semiconductor substrate is divided into a number of active and isolation regions through an isolation process, such as, field oxidation or shallow trench isolation. A thin oxide is grown on an upper surface of the semiconductor substrate in the active regions. The thin oxide serves as the gate oxide for subsequently formed transistors.
Polysilicon gate conductors are formed in the active regions above the thin oxide. The gate conductor and thin oxide form a gate structure which traverses each active region, effectively dividing the active region into two regions referred to as a source region and. a drain region. After formation of the polysilicon gates, an implant is performed to introduce an impurity distribution into the source/drain regions. Generally, source/drain regions are heavily doped with n-type or p-type dopants.
Often a source extension and drain extension are disposed partially underneath the gate structure to enhance transistor performance. Source and drain extensions are extensions of the source and drain regions. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both n-channel and p-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering.
Spacers are structures which abut lateral sides of the gate structure and are provided over source and drain extensions. Preferably, spacers are silicon dioxide (SiO
2
) structures. Alternatively, other spacer materials, such as, silicon nitride (Si
3
N
4
), silicon oxynitride (SiON), or other insulators can be used. Conventional spacer formation tends to have a rounded shape in cross-section. Traditionally, metal oxide semiconductor (MOS) field effect transistors (FETs) utilize a D-shaped spacer, a triangle shaped oxide spacer, or a trapezoid shaped nitride spacer. The spacer helps to separate the shallow source and drain extensions from the deep source and drain contact junctions. With a different shape of the conventional spacer, it is possible to improve design flexibility and improve device manufacturability.
Thus, there is a need for a method of forming L-shaped nitride spacers. Further, there is a need for an additional buffer to the source and drain extension that makes the best tradeoff between series resistance and short-channel effect. Even further, there is a need for increased possibilities in integrated circuit device design.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of forming L-shaped spacers in an integrated circuit. This method can include providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, forming dummy oxide spacer structures over the spacer material where the dummy oxide spacer structures are shaped to selectively cover an L-shaped portion of the spacer material, removing portions of the spacer material not covered by the dummy oxide spacer structures, and removing the dummy oxide spacer structures.
Another embodiment relates to a method of forming cross-sectionally L-shaped spacers in an integrated circuit. This method can include forming a gate structure on a substrate, depositing a liner oxide layer over the substrate and the gate structure, depositing a nitride layer over the liner oxide layer, forming dummy oxide spacer structures over the nitride layer where the nitride layer is located proximate lateral side walls of the gate structure, and removing portions of the nitride layer and liner oxide layer not covered by the dummy oxide spacer structures.
Another embodiment relates to a method of fabricating an integrated circuit. This method can include depositing a layer of spacer material over a semiconductor substrate and a gate structure disposed over the semiconductor substrate, providing dummy spacer structures over first portions of the layer of spacer material, removing second portions of the layer of spacer material, and removing the dummy spacer structures. The first portions of the layer of spacer material are L-shaped and are located proximate lateral side walls of the gate structure. The second portions of the layer of spacer materials are uncovered by the dummy spacer structures.
Other features and advantages of embodiments of the present invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
REFERENCES:
patent: 5770508 (1998-06-01), Yeh et al.
patent: 6156598 (2000-12-01), Zhou et al.
patent: 6235597 (2001-05-01), Miles
patent: 6294480 (2001-09-01), Pradeep et al.
Advanced Micro Devices , Inc.
Foley & Lardner
Lindsay Jr. Walter L.
Niebling John F.
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