Static random access memory manufacturing method

Details Static random access memory manufacturing method Static random access memory manufacturing method

2001-08-31

2002-08-27

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S526000

Reexamination Certificate

active

06440804

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90118008, filed on Jul. 24, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a random access memory (RAM) manufacturing method. More particularly, the present invention relates to a static random access memory (SRAM) manufacturing method.
2. Description of the Related Art
RAM is a volatile memory, wherein SRAM uses the conducting conditions of a memory cell internal chip to store material. SRAM is specially characterized by high speed operation, low power consumption and simple operation. Thus, SRAM is advantageous since the design is simple and it does not need to often renew the data for access. Generally, within the SRAM, the contact windows connecting the gate electrode and the interconnect is usually a buried contact window.
FIGS. 1A
to
1
D are diagrams in cross-sectional view of a conventional SRAM manufacturing method.
Referring to
FIG. 1A
, a substrate with a pre-formed gate oxide layer
102
and a first polysilicon layer
104
is defined. A buried contact window opening
106
is formed and exposes the substrate
100
.
Referring to
FIG. 1B
, a second polysilicon layer
108
is formed upon the substrate
100
and covers the buried contact window opening
106
. An implantation procedure
110
is performed and forms a buried contact window
112
.
Referring to
FIG. 1C
, a photoresist layer
114
is formed upon the substrate
100
. The photoresist layer
114
is patterned. In this manner, the thickness of the polysilicon layer at the regions
120
and
122
can be observed.
Referring to
FIG. 1D
, using the patterned photoresist layer
114
as a mask, etching is performed on the first and second polysilicon layers
104
and
108
, thereby forming a gate electrode
116
and an interconnect
118
.
However, in the above-described process of the related art, during the etching procedure of the gate electrode
116
and the interconnect
118
, as seen in
FIG. 1C
, there is a difference in thickness between the polysilicon layer in the region
120
and the region
122
. Thus, after the entire removal of the first polysilicon layer
108
in the region
120
, at least a portion of the second polysilicon layer
104
in region
122
has still not been etched away. Thus, when continuously etching away the second polysilicon layer
104
, a trench
124
such as the one shown in
FIG. 1D
is formed. When the depth of the trench
124
in the substrate
100
exceeds the depth of the buried contact window
112
, the buried contact window
112
is broken. An open circuit occurs between the successively formed device source/drain and the buried contact window
112
.
SUMMARY OF THE INVENTION
The invention provides a SRAM manufacturing method. An occurrence of a silicon trench is prevented and an open circuit between the device source/drain and the buried contact window beneath the buried window is prevented.
As embodied and broadly described herein, the invention provides a SRAM manufacturing method. A substrate with a pre-formed gate oxide layer and a first conducting layer is defined, thereby forming a buried contact window opening and exposing the substrate. A second conducting layer is formed upon the substrate and covers the buried contact window opening. An implantation procedure is performed on the second conducting layer. A thermal annealing process is performed, causing the dopant within the second conducting layer to disperse into the substrate, thereby forming a buried contact window within the substrate. Using a spin coating technique, an oxide layer is formed on the substrate and the contact window is filled in. A portion of the oxide layer is removed, causing the top of the oxide layer to be level with the top of conducting layer. Using the second conducting layer as an etch stop layer, an etching back process is performed on the oxide layer. A photoresist layer is formed upon the substrate and the photoresist layer is patterned thereafter. Using the photoresist layer as a mask, the exposed second conducting layer is removed. By continuously etching away the first conducting layer beneath the second conducting layer, a gate electrode and an interconnect are formed. The patterned photoresist layer is removed. The oxide layer can be either removed or retained. A second implantation layer is performed to form a source/drain of the gate electrode, causing the source/drain and the buried contact window to connect to each other.
The advantage of the present invention is that a local planarization protective layer is formed using such a technique as spin coating. Since there are numerous etching options for the protective layer and the etched polysilicon layer, the protective layer is not easily removed and can be used as a mask. The successively formed device source/drain are specially characterized by self-alignment. During etching of the gate electrode, over-etching of the substrate due to different thicknesses of the etched layers is prevented, trench formations do no occur and open circuit between the device source/drain and the buried contact window is prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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patent: 5391905 (1995-02-01), Yamazaki
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patent: 6022794 (2000-02-01), Hsu
patent: 6150267 (2000-11-01), Chen
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