Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-14
2002-12-24
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000
Reexamination Certificate
active
06498064
ABSTRACT:
The present invention relates to a semiconductor device, and more specifically, to a flash memory having high coupling ratio and the method of fabricating the nonvolatile memory.
BACKGROUND OF THE INVENTION
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Further, it can be used to replace magnetic disk memory. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMs.
Different types of devices have been developed for specific applications requirements in each of the segments of memory. In the device, electrical alterability is achieved by Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-thin dielectric interface and into the oxide conduction band. Typically, the thin dielectric layer is composed of silicon dioxide and the thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide and remain trapped there since the materials are high quality insulators. A conventional flash memory is a type of erasable programmable read-only memory (EPROM). One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, the speed of memory erasure is fast. For other EPROM, the memory erasure can take up to several minutes due to the erase mode of such type memory is done by bit-by-bit.
Various flash memories have been disclosed in the prior art, the type of the flash includes separated-gate and stacked-gate structure. U.S. Pat. No. 6,180,454 to Chang, et al, entitled “Method for forming flash memory devices”, and filed on Oct. 29, 1999. U.S. Pat. No. 5,956,268 disclosed a Nonvolatile memory structure. The prior art allows for array, block erase capabilities. U.S. Pat. No. 6,153,494 to Hsieh, et al., entitled “Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash” and filed on Feb. 11, 1998. The object of this invention is to provide a method of forming a stacked-gate flash memory having a shallow trench isolation with a high-step in order to increase the lateral coupling between the word line and the floating gate. Hsieh disclosed a step of forming nitride layer and then forming hallow trench isolation (STI) through the nitride layer into the substrate. Then, oxide is filled into the STI, the nitride is then removed leaving behind a deep opening about the filled STI. The detailed description may refer to the prior art. A stacked-gate flash memory cell is provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.
Chen disclosed a nonvolatile memory with self-aligned floating gate in U.S. Pat. No. 6,140,182 and assigned to Actrans System Inc. A further prior art can be seen in U.S. Pat. No. 6,172,396 to Chang, the prior art provides a method that is capable of eliminating buried trenches in the source/drain regions without lowering the coupling rate between the floating gate and the control gate.
SUMMARY OF THE INVENTION
The object of the present invention is to form flash memory with higher coupling ratio.
It is another object of this invention to provide a method of forming a flash memory having sidewall coupling to increase the coupling ratio between the control gate and the floating gate of the cell.
The flash memory according to the present invention comprises a substrate having trenches formed therein. A tunneling oxide is formed on a surface of the substrate and adjacent to the trenches. A raised isolation fillers is formed in the trenches and protruding over an upper surface of the substrate, thereby forming a cavity between two adjacent raised isolation fillers. A floating gate is formed along a surface of the cavity to have a U-shaped structure in cross sectional view, wherein the high level of the U-shaped structure is the same with the one of the raised isolation fillers. An isolation structure is formed on the top of the raised isolation fillers and upper surface of the U-shaped structure. A dielectric layer conformally is formed on a surface of the floating gate and the isolation structure. A control gate is formed on the dielectric layer.
A method of manufacturing a flash memory comprises forming a first dielectric layer on a semiconductor substrate and patterning the first dielectric layer, the substrate to form trenches in the substrate. First isolations is refilled into the trenches, followed by removing the first dielectric layer, thereby forming a cavity between the first isolations and the isolations protruding over the substrate. A tunneling oxide is formed on the substrate, then a first conductive layer is formed on the tunneling oxide and along a surface of the first isolation. A second dielectric layer is formed on the first conductive layer. A portion of the second dielectric layer is removed to expose the first conductive layer on the first isolation. An oxidation is performed to transform the exposed first conductive layer into second oxide, thereby separating the first conductive layer. A third dielectric layer is formed on a surface of the first conductive layer. A second conductive layer is formed on the second dielectric layer as a control gate.
REFERENCES:
patent: 5599727 (1997-02-01), Hakozaki et al.
patent: 2001/0002714 (2001-06-01), Doan
Blakely , Sokoloff, Taylor & Zafman LLP
Booth Richard
Vanguard International Semiconductor Corporation
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