Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-30
2002-12-17
Lee, Eddie (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S304000, C257S311000
Reexamination Certificate
active
06495876
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to formation of a low resistive strap with hydrogen annealing within a DRAM structure.
2. Description of the Related Art
Conventional processing of trench dynamic random access memory (DRAM) structures forms a buried strap during the formation of a deep trench to connect the conductor in the deep trench to an adjacent transistor. The strap resistance has been shown to be a significant bottleneck in trench DRAM characteristics. The primary reason for this is that the active area (AA) to deep trench (DT) overlay is limited (by tool capability) to about 45 nm. The conventional process causes the strap to be etched away around the trench in unwanted areas during the shallow trench isolation definition leaving a sliver of silicon along the trench sidewalls to contact to the deep trench portion below the STI. This contributes significantly to the strap resistance.
Various schemes have been proposed (sometimes with an oxide cap on top of the trench as by Radens et al., U.S. Ser. No. 09/272124, referred to as a ‘Pedestal’ STI) leaving the polysilicon in the trench untouched but etching only the silicon outside the trench or performing the strap recess after the active area (AA) etch with a ‘Poly Planarized’ STI etch. However, neither of these schemes work with a ‘lip’ or near surface strap which is deemed necessary to avoid a deep strap with poor array device performance.
It should also be noted that for deep trenches with high cell capacitance it is necessary to minimize the gap at the top of the trench. However, the conventional poly fill technology cannot fill perfectly vertical trenches. This constant tradeoff results quite often with voids in the top of the trench polysilicon which need to be healed to prevent them from opening up during shallow trench isolation etching.
Therefore, there is a need for a low resistance buried strap which is thicker and does not have trench voids. It is to be noted that rounding of the STI corners is preferable for good gate oxide integrity.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the transistor, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprises a collar oxide extending into the shallow trench isolation region on the second side. A method of manufacturing a DRAM device includes depositing a conductor in a trench, removing a portion of the conductor to form a shallow trench isolation region, and reflowing the conductor to form a curve in the conductor adjacent the shallow trench isolation region. The reflowing comprises hydrogen annealing, the curve is convex, or concave. The reflowing increases the width of the conductive portion. The trench has a collar oxide to surround a top portion of the conductor whose removal is selective to the collar and leaves the collar oxide in place. The collar oxide contacts a shape and position of the curve, further comprising forming a transistor adjacent the trench, wherein the top portion of the conductor comprises a strap connecting the conductor to the transistor and the curve reduces the resistance of the strap.
REFERENCES:
patent: 5362575 (1994-11-01), Trimble
patent: 5494860 (1996-02-01), McDevitt et al.
patent: 5508541 (1996-04-01), Hieda
patent: 5895274 (1999-04-01), Lane et al.
patent: 0 987 754 (2000-03-01), None
patent: 2000-58774 (2000-02-01), None
IBM Technical Disclosure Bulletin, T.V. Rajeevakumar, “Process Scheme to Make Shallow Trench Isolation Self-Aligned to the Storage Trench,” vol. 33, No. 10A, pp. 260-262, Mar. 1991.
Bronner Gary
Divakaruni Ramachandra
Takegawa Yoichi
Blecker Ira D.
Lee Eddie
McGinn & Gibb PLLC
Pizarro-Crespo Marcos D.
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