Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-05-15
2002-11-19
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S608000, C438S650000, C438S687000, C427S125000, C427S126100, C427S126300, C427S126500, C427S126600
Reexamination Certificate
active
06482740
ABSTRACT:
The present application claims the benefit under 35 U.S.C. §119(a) of Finnish Patent Application No. 20001163, filed May 15, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the manufacturing of integrated circuits (ICs), and particularly to the seed layers in damascene and dual damascene processes, gate metals of thin film transistors and capacitor electrodes in ICs.
More particularly the present invention relates to a method of depositing seed layers for a damascene and dual damascene structures, gate metals of thin film transistors and capacitor electrodes in ICs by an atomic layer deposition (ALD) method.
2. Description of the Related Art
The atomic layer deposition (ALD) method of depositing thin films has several attractive features including excellent step coverage, even on large areas, and a dense and pinhole-free structure. Therefore, it is of great interest to apply ALD to the deposition of metallization layers of advanced integrated circuits (ICs), where the continuously increasing packing density and aspect ratio set higher and higher demands upon the metallization layers. Applications where high quality metallization is particularly needed are dual damascene structures, gates in transistors and capacitors in ICs. However, due to the fact that ALD is based on sequential self-saturating surface reactions of source chemical compounds, depositing high quality elemental metal thin films by ALD is very difficult.
In ALD, the source chemical molecules chemisorb on the substrate via active sites on the substrate surface. Typical active sites for metal source chemicals are —OH, —NH
2
and >NH groups. Metal-oxygen-metal bridges on the surface may also act as active sites. When a metal source chemical molecule reacts with the active site, a strong bond is formed between the surface and the ligand of the source chemical molecule is simultaneously released as a by-product.
In ALD, films grow with a constant growth rate. Each deposition cycle produces one molecular layer of the deposited material on the substrate surface. Usually the growth rate is well below one molecular layer/cycle because the adsorbed source chemical molecules may be bulky or because substrate temperature affects the number of active sites (e.g. —OH groups) on the surface. It is well known that metal oxide thin films produced by ALD are uniform, have excellent adhesion and thus are firmly bonded to the substrate surface.
Experiments have revealed a drawback of the growth of metal thin films by an ALD type method. In the case of metal deposition it is difficult to attach source chemical molecules to the surface because essentially no active sites exist on the surface. The metal film grown is often non-uniform over an area of the substrate and it is easily peeled off from the surface, which indicates very poor adhesion of the film to the substrate.
Several attempts have been made to produce metal thin films by ALD type methods. Reproducibility of such an ALD metal growth process has traditionally been poor and the reactions do not take place at all on insulating surfaces like silicon oxide. There are publications about the ALD deposition of Cu metal by pulsing a copper compound, e.g. Cu(thd)
2
, on a surface and then reducing the Cu(thd)
2
molecules bound to the surface into Cu with H
2
.
R. Solanki et al. (Electrochemical and Solid-State Letters 3 (2000) 479-480) have deposited copper seed layers by ALD. They deposited copper directly from alternate pulses of bis(1,1,1,5,5,5-hexafluoroacetylacetonato)copper(II)hydrate and either methanol, ethanol or formalin, i.e. a water solution of formaldehyde. The total pulsing cycle time was 64 s, i.e. slightly over one minute. Although the growth rate was not mentioned in the publication, a typical growth rate of a thin film made by ALD from metal &bgr;-diketonates is 0.03 nm/cycle due to the steric hindrance of the source chemical molecules. Thus, the deposition time for a 10 nm copper seed layer would be over 5 hours, which is uneconomical for wafer processing. A required minimum throughput of a wafer reactor is 10-12 wafers/hour. It is to be noted that according to Strem Chemicals, Inc. the decomposition temperature of the copper compound used by R. Solanki et al. is 220° C. R. Solanki et al. noticed copper film growth when the substrate temperature was 230-300° C. Therefore, partial thermal decomposition of copper source compound on substrate surface is probable.
One of the most advanced IC structures is the dual damascene structure which consists of a silicon substrate with transistors (source, gate and drain). Several electrically conducting layers are needed in the structure. The first metallization level is done with tungsten plugs and aluminium interconnects to prevent the contamination of the gate with copper. The remainder of the metallization levels are made of copper.
The process steps of a dual damascene process are described below.
Step 1. A silicon nitride etch stop is grown on the previous metallization surface.
Step 2. A via level dielectric is deposited.
Step 3. Another silicon nitride etch stop is deposited.
Step 4. A trench level dielectric is deposited. SiO
2
has been favoured as the dielectric material. Low-k materials such as nitrided silicon oxide and polymers have been experimented with as an alternative dielectric material.
Step 5. Patterning of dielectric by photolithography.
a. A resist layer is deposited on dielectrics surface.
b. The resist layer is patterned and the resist is removed from the via areas.
c. Dielectrics are etched from the via areas with directional plasma. Etching terminates at the silicon nitride surface.
d. Resist is stripped from the surface.
Step 6. Patterning of the etch stop layer by photolithography.
e. A second resist layer is deposited on the surface.
f. The resist layer is patterned and it is removed from the trench areas.
g. Silicon nitride is removed with a short plasma nitride etch from the bottom of the holes that were made with the first plasma oxide etch.
h. The second plasma oxide etch removes silicon dioxide from the exposed via and trench areas until the first silicon nitride etch stop is reached.
i. The first silicon nitride etch stop is removed from the via bottom and the second silicon nitride etch stop from the trench bottom with a short plasma nitride etch.
j. The resist is stripped from the substrate.
Step 7. A diffusion barrier layer is grown on all exposed surfaces.
Step 8. A seed layer for copper deposition is grown with CVD or PVD on the diffusion barrier layer.
Step 9. Vias and trenches are filled with copper by an electroplating process.
Step 10. The substrate surface is planarized with chemical mechanical polishing (CMP). The surface is polished until copper and a barrier layer are left only in trenches and vias.
Step 11. The surface is capped with a silicon nitride etch stop layer.
Step 12. The metallization process is then repeated for all the remaining metallization levels.
Alternatives for copper electroplating (Step 9) are electroless plating, physical vapor deposition (PVD) and chemical vapor deposition (CVD). A seed layer (c.f Step 8) is only needed for the electroplating process. Traditionally such a seed layer is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In the electroplating process the substrate having an electrically conductive seed layer is immersed in a metal compound solution. The electrically conductive surface of the substrate is connected to an external DC power supply. A current passes through the substrate surface into the solution and metal is deposited on the substrate. The seed layer has high conductivity and it acts as a conduction and nucleation layer for the electroplating process. One can envision a seed layer that acts as a nucleation layer for the CVD process. The seed layer carries current from the edge of the wafer to the center of the wafer and from the top surface of the wafer into the bottom of vias and trenches. A uniform and continuous seed layer is necessar
Elers Kai-Erik
Haukka Suvi
Soininen Pekka J.
ASM Microchemistry Oy
Everhart Caridad
Knobbe Martens Olson & Bear LLP
Lytle Craig P.
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