Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-03
2002-06-18
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S742000
Reexamination Certificate
active
06408412
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method and structure for testing embedded cores in a system-on-a-chip (SoC) IC, and more particularly, to a method and structure for testing analog/mixed signal cores in a microprocessor based system-on-a-chip (SoC) IC.
BACKGROUND OF THE INVENTION
In recent several years, ASIC (application specific integrated circuit) technology has evolved from a chip-set philosophy to an embedded core based system-on-a-chip (SoC) concept. An SoC IC includes various reusable functional blocks, such as microprocessors, interfaces, memory arrays, and DSPs (digital signal processors). Such pre-designed functional blocks are commonly called “cores”.
FIG. 1
is a schematic diagram showing an example of inner structure of such an SoC IC. In the example of
FIG. 1
, an SoC IC
10
includes a microprocessor core
12
, memory cores
13
-
16
, function specific cores
21
-
23
, a phase lock loop (PLL) core
25
, a test access port (TAP)
26
, an A/D (analog-to-digital) and D/A (digital-to-analog) core
27
, a PCI (interface) core
28
, and a glue logic (support logic such as I/O). How to test such embedded cores is a new and complex problem in IC testing. The present invention is directed to a method and structure for testing such embedded cores, particularly, analog and/or mixed-signal cores, such as an analog-to-digital converter (ADC) and a digital-to-analog (DAC) converter in an SoC IC.
Testing of embedded analog/mixed-signal cores is considered a difficult problem in an SoC IC testing. In general, various design-for-test (DFT) schemes are used to access the embedded analog blocks such as digital-to-analog converters (DAC) and analog-to-digital converters (DAC), while the testing is performed by specialized hardware such as mixed-signal automatic test equipment (ATE) or an IC tester. The difficulty in testing embedded analog/mixed signal blocks is two-fold; first the access to the analog blocks so that test stimuli can be applied, and second observing the response of the analog blocks for evaluation. This difficulty is further enhanced due to the fact that these blocks require an analog signal as test input or their response output is an analog signal. Thus, a simple binary comparison cannot be conducted in testing.
In the conventional technology, as noted above, specialized mixed-signal test equipment such as a mixed-signal IC tester has been used to test the analog and mixed-signal blocks such as DACs and ADCs. The testing method is the same regardless of whether it is a monolithic DAC/ADC or embedded DAC/ADC. While the access to inputs and outputs in a monolithic DAC/ADC has been through the primary input-output pins, the test point insertion and design for test (DFT) logic have been used to access the input-outputs of embedded DAC/ADCs.
An offset voltage (Vos), full-scale range (FSR), all code values particularly missing codes and major transitions, differential non-linearity (DNL) and integral non-linearity (INL), etc. are the key parameters that are tested for DAC/ADCs. The generally used test methods for measuring the code transition levels to evaluate these parameters are an AC histogram method, a ramp histogram method and a code density test method.
In all the conventional approaches, a dedicated hardware has been used on a load-board near the device under test (DUT) in the ATE system. When the testing is performed by a mixed signal IC tester, the tester pin interface circuitry has been used for test pattern application and measurements while the response evaluation is done by the tester software. In some research projects on analog built-in self-test methods, dedicated on-chip hardware has been used for test generation and response evaluation (B. Dufort and G. W. Roberts, “On-chip analog signal generation for mixed-signal built-in self-test”, IEEE J. Solid Stated Circuits, pp. 318-330, March 1999). However, such conventional methods require a substantial amount of additional hardware (overhead), resulting in the production efficiency decrease and the cost increase. Further, such hardware overhead causes a performance penalty, for example, a signal propagation delay.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method and structure for testing embedded analog and/or mixed-signal cores in a system-on-a-chip (SoC) IC, with substantially no increase in the hardware overhead in the SoC IC.
It is another object of the present invention to provide a method and structure for testing embedded analog/mixed-signal cores in a system-on-a-chip (SoC) IC, with substantially no performance disadvantage to the SoC IC.
It is a further object of the present invention to provide a method and structure for testing embedded analog/mixed signal cores in a system-on-a-chip (SoC) IC with high test efficiency and low cost.
One aspect of the present invention is a method of testing embedded analog cores in an integrated circuit chip having a microprocessor core and a memory core therein. The method is comprised of the steps of: providing a test register in the integrated circuit chip between the microprocessor core and an analog core to be tested; testing the microprocessor core and the memory core; using an assembly language test program running on the microprocessor core to generate a test pattern by the microprocessor core; applying the test pattern to the analog core by the microprocessor core and evaluating the response of the analog core either by the microprocessor core or a test system provided outside of the integrated circuit chip.
In the above test method, the microprocessor core first tested by executing microprocessor instructions multiple of times with pseudo random data and evaluating the results. The memory core is then tested by the microprocessor core which generates a memory test pattern and applies the memory test pattern to the memory core and evaluates the stored data in the memory core. The foregoing testing of the microprocessor core and memory core is the subject in the separate patent applications, U.S. application Ser. Nos. 09/170,179, 09/182,382 and 09/183,033 filed by the same inventors of the present invention.
Another aspect of the present invention is a structure for testing analog/mixed-signal cores. The structure is comprised of: a test register formed in the integrated circuit chip between the microprocessor core and an analog core to be tested, a multiplexer provided between the test register and the analog core for selectively providing data to the analog core; means for executing microprocessor instructions multiple times and evaluating the results to ensure integrity of the microprocessor core and for testing a memory core by generating a memory test pattern by the memory core and evaluating the results; and a host computer for providing an executable test program to the microprocessor core through an interface circuit; wherein the analog core is provided with a test pattern generated by the microprocessor core and the resultant output of the analog core is evaluated by either the microprocessor core or the host computer.
According to the present invention, the test method does not require large area overhead (it requires only a register and a multiplexer in a system-on-a-chip IC). Because the hardware overhead is negligible, the new test method causes no performance penalty. The present invention can avoid specialized test equipment and hence does not require dedicated observation and control points to be built in the design of the SoC IC. This method is applicable to standard product DAC/ADCs, as well as embedded analog/mixed signal cores in a microprocessors based system-on-a-chip.
REFERENCES:
patent: 5963566 (1999-10-01), Rahsynab et al.
patent: 5991898 (1999-11-01), Rajski et al.
patent: 6249893 (2001-06-01), Rajsuman et al.
Advantest Corp.
Chung Phung M.
Muramatsu & Associates
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