Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-12
2002-08-20
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000, C438S279000, C438S286000, C438S287000, C438S528000, C438S591000, C438S981000
Reexamination Certificate
active
06436771
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method of fabricating a semiconductor device featuring the formation of multiple gate dielectric layers, with various gate dielectric thicknesses, for the multiple elements of the semiconductor device.
(2) Description of Prior Art
The use of complimentary metal oxide semiconductor (CMOS), devices for semiconductor integrated circuit applications, has resulted in the fabrication of both N channel (NMOS), as well as P channel (PMOS), type devices, on the same semiconductor chip, sometimes necessitating a gate dielectric layer for one type channel device different in thickness than the gate dielectric thickness used for the counterpart type device. In addition specific elements in the integrated circuit may demand a specific gate dielectric thickness, again different from the thicknesses used for other type elements of the semiconductor design. A specific thickness of the gate dielectric layer may be needed to optimize the parametrics of that specific element, and thus the performance of the integrated circuit can be influenced by the ability to form several different gate dielectric thicknesses, for the various elements residing on the same semiconductor substrate.
To successfully form multiple thickness, gate dielectric layers, such as thermally grown silicon dioxide layers, on the same semiconductor substrate, the thin gate dielectric layer sometime needs to be formed on a region of the semiconductor substrate that had just been subjected to an HF type solution. The HF solution is used to remove a thick silicon oxide component, used as a gate dielectric layer for a first type element, from an area of the A semiconductor substrate to be used for a second device or element, needing a thinner gate dielectric layer. This sequence can present several shortcomings such as the HF solution finding defects in a photoresist shape used to protect the thicker silicon dioxide gate dielectric component, thus etching pin holes in the thicker gate dielectric layer resulting in subsequent gate shorts or leakage. In addition the thickness needed for the regrown, thinner silicon oxide gate dielectric layer, on the bare portion of semiconductor may be difficult to control when directly growing this thin silicon dioxide layer on a bare semiconductor substrate.
This invention will describe several novel fabrication sequences in which multiple thicknesses for gate dielectric layers are obtained without risking HF attack of the thicker silicon dioxide gate dielectric layer, and also improving the ability to control the thickness of the thin silicon dioxide gate layer. Prior art, such as Holloway et al, in U.S. Pat. No. 5,989,962, as well as Chau, in U.S. Pat No. 6,048,769, describe process sequences and materials used to fabricate gate dielectric layers, with different thicknesses, on the same semiconductor substrate. However these prior arts do not describe the novel process steps, and composite gate dielectric components, used in this present invention.
SUMMARY OF THE INVENTION
It is an objective of this invention to fabricate metal oxide semiconductor field effect transistor (MOSFET), elements on a semiconductor substrate, wherein first gate dielectric layers, at a specific thickness, are formed for first MOSFET elements, while second gate dielectric layers, formed at thicknesses different than the thickness used for the first dielectric layers, are used for second MOSFET elements.
It is another object of this invention to perform a remote plasma nitridization procedure on a first silicon dioxide gate layer located on a first portion of a semiconductor substrate, and on a bare, second portion of the semiconductor substrate, prior to controllably forming a second silicon dioxide gate layer, on the second portion of the semiconductor substrate, with the second silicon dioxide gate layer thinner in thickness than the first silicon dioxide gate layer.
It is still another object of this invention to thermally grow a thin silicon dioxide gate layer on a bare, second portion of a semiconductor substrate, while a thicker, composite silicon nitride—silicon dioxide layer, resides on a first portion of the semiconductor substrate.
In accordance with the present invention methods of forming gate dielectric layers on a first portion of a semiconductor substrate, at a first thickness, while simultaneously forming other gate dielectric layers, at a second thickness, on a second portion of the semiconductor substrate, are described. A first iteration of this invention entails the thermal growth of a first silicon dioxide layer, at a first thickness, on a semiconductor substrate. After removal of the first silicon dioxide layer, from a first portion of the semiconductor substrate, a remote plasma nitridization procedure is performed resulting in the formation of a thin silicon nitride layer on the first portion of the semiconductor substrate, while a thin silicon oxynitride layer is formed on the first silicon dioxide layer, located on a second portion of the semiconductor substrate. A thermal oxidation procedure is then performed to grow a thin, second silicon dioxide layer on the first portion of the semiconductor substrate, underlying the thin silicon nitride layer, while the first silicon dioxide layer, located on the second portion of the semiconductor substrate, underlying the silicon oxynitride layer, increases in thickness, with the re-oxidized, first silicon dioxide layer greater in thickness than the second silicon dioxide layer. A second iteration of this invention employs a composite dielectric layer, comprised of silicon nitride on silicon dioxide, on a first portion of a semiconductor substrate, while the same composite dielectric layer is removed from a second portion of the semiconductor substrate. A thermal oxidation procedure is then employed to grow a thin silicon dioxide layer on the second portion of the semiconductor substrate, while the thickness of the composite dielectric layer, located on a first portion of the semiconductor substrate remains unchanged.
REFERENCES:
patent: 5254489 (1993-10-01), Nakata
patent: 5716863 (1998-02-01), Arai
patent: 5763922 (1998-06-01), Chau
patent: 5989962 (1999-11-01), Holloway et al.
patent: 6048769 (2000-04-01), Chau
patent: 6093661 (2000-07-01), Trivedi et al.
patent: 6171911 (2001-01-01), Yu
Jang Syun-Ming
Liang Mong-Song
Yu Chen-Hua
Ackerman Stephen B.
Chaudhari Chandra
Chen Jack
Saile George O.
Taiwan Semiconductor Manufacturing Company
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