Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2001-04-11
2002-08-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S041000
Reexamination Certificate
active
06437597
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to automatic test equipment for programmable logic devices, and in particular to methods and circuits for precisely placing signal transitions on the input pins of programmable logic devices.
BACKGROUND
Most semiconductor devices are tested at least once using some form of automated test equipment (generally, a “tester”). Testers generally have a “per-pin” architecture in which separate “channels” within the tester generate or measure one signal corresponding to a single input or output pin on a device under test (DUT). Each channel is separately controlled to generate or measure a different signal. A pattern generator, the function of which is to send commands to each channel to generate or measure one test signal for each of many test periods, controls the various channels. Each channel generally contains at least one edge generator programmed to generate a signal transition, or “edge,” at a certain time relative to the start of each test period.
Testers must place accurately timed edges at the various pins of a device under test to make accurate pin-to-pin measurements. When properly calibrated, testers with hundreds or even thousands of channels are only able to reduce the relative error between channels to somewhere in the range of ±500 ps to ±1 ns. All measurements require at least two edges be placed, so the cumulative measurement error inherent in the tester can contribute somewhere between 1 ns and 2 ns of uncertainty. Unfortunately, this inherent tester error often exceeds the value of the parameter being measured. To make matters worse, the test boards used to connect the tester channels to device pins can contribute different delays for different channels, adding to the timing uncertainty. There is therefore a need for a means of more precisely placing edges on the pins of devices under test.
A number of engineers employed by Xilinx, Inc., the assignee of the present application, addressed the need for a more precise means of placing edges. The resulting invention is described in U.S. patent application Ser. No. 09/737,996 entitled “Circuit For Measuring Signal Delays of Synchronous Memory Elements,” by Siuki Chan and Christopher H. Kingsley, which is incorporated herein by reference. A relevant portion of that application is reproduced below in connection with
FIGS. 1-3
.
FIG. 1
depicts a conventional tester
100
connected to a device under test (DUT)
110
. In the example, DUT
110
is a field programmable gate array (FPGA). DUT
110
includes a coincidence detector
120
that can be used to calibrate tester
100
to produce coincident edges on device input pins
125
A and
125
B, two of the many pins
125
on DUT
110
.
Coincidence detector
120
connects to three input paths A, B, and R and an output path OUT. These four paths connect to respective tester leads
130
A,
130
B,
130
R, and
130
Q through respective device pins. Coincidence detector
120
includes an XOR gate
135
and a flip-flop
140
. Tester
100
initializes coincidence detector
120
by presenting a positive pulse on lead
130
R, thus resetting flip-flop
140
.
In one embodiment, DUT
110
is a Virtex™ FPGA available from Xilinx, Inc., of San Jose, Calif. Virtex™ FPGAs include configurable logic blocks that can be configured to instantiate coincidence detector
120
. For more information about Virtex™ and other types of FPGAs for use with the invention, see, for example, pages 3—3 thru 3-22 and 4-3 thru 4-69 of “The Programmable Logic Data Book,” (1999) from Xilinx, Inc., incorporated herein by reference.
FIG. 2A
is a waveform diagram
200
illustrating the case in which simultaneous edges of the same polarity are presented on each of pins
125
A and
125
B. As is conventional, XOR gate
135
outputs a logic one if the signals on input paths A and B have opposite logic levels (i.e., A=1 and B=0 or A=0 and B=1). Because each of the signals on paths A and B transition at the same instant in
FIG. 2A
, the logic levels on paths A and B are always the same. The output of XOR gate
135
therefore remains a logic zero. Output path OUT also remains at logic zero in the absence of a positive-going edge to clock the flip-flop.
FIG. 2B
is a waveform diagram
210
illustrating an edge (i.e., signal transition)
215
on path A arriving before an edge
220
on path B. XOR gate
135
will output a logic one during the time separating edges
215
and
220
when the signals on paths A and B are at opposite logic levels. The positive-going edge
225
on the output of XOR gate
135
will clock flip-flop
140
, causing flip-flop
140
to store the logic one on data terminal D and to output the stored level on output path OUT. The logic one on output path OUT indicates that edges
215
and
220
are not coincident.
FIG. 2C
is a waveform diagram
230
illustrating an edge
235
on path A arriving before an edge
240
on path B. The edges are closer than in
FIG. 2B
, so XOR gate
135
outputs a logic one for a shorter period. The short pulse is still sufficient to clock flip-flop
140
, so flip-flop
140
outputs a logic one, indicating that edges
235
and
240
are not coincident.
FIG. 2D
is a waveform diagram
250
illustrating an edge
255
on path A arriving only slightly before an edge
260
on path B. The signal transitions are spaced far enough apart so that XOR gate
135
exhibits a small voltage spike
265
. However, the small spike is insufficient to clock flip-flop
140
, and therefore does not affect a change on line OUT. Thus, coincidence detector
120
will indicate coincident signals although edges
255
and
260
are not exactly coincident. The maximum delay between edges for which coincidence detector
120
indicates coincidence determines the resolution of coincidence detector
120
, and may vary considerably depending upon the selected type of coincidence detector.
FIG. 3
is a flowchart
300
illustrating a method for estimating the skew between pins
125
A and
125
B of FIG.
1
. First coincidence detector
120
is instantiated on DUT
110
(step
305
). In an embodiment in which DUT
110
is an FPGA, coincidence detector
120
can be created from configurable logic using conventional FPGA programming techniques.
Tester
100
places edges on each of pins
125
A and
125
B (step
310
). These edges are spaced sufficiently in time to ensure coincidence detector
120
indicates the signals are not coincident. In the example of
FIG. 3
, the edge on pin
125
A leads the edge on pin
125
B. Then, using the following sequence of steps, the spacing between the two edges is reduced incrementally until coincidence detector
120
indicates the edges are coincident.
Assuming the edges are sufficiently spaced for coincidence detector
120
to output a logic one (decision
315
), the channel in tester
100
corresponding to pin
125
A is adjusted to move the leading edge on pin
125
A toward the trailing edge on pin
125
B (step
320
). Adjusting the delay associated with a given channel is well within the skill of those familiar with operating testers. Coincidence detector
120
is then reset and the process returns to step
310
in which the new pair of edges, now more closely spaced, are presented on pins
125
A and
125
B.
By cycling through steps
310
,
315
, and
320
, the delay separating the edges on pins
125
A and
125
B is incrementally reduced until coincidence detector
120
indicates that the two edges are coincident (in decision
315
). The relative timing of the two edges (i.e., the first skew data) is then recorded (step
325
), in memory within tester
100
, for example.
Next, tester
100
again places edges on each of pins
125
A and
125
B (step
330
). This time, however, the edge on pin
125
A is set to trail the edge on pin
125
B by an amount sufficient to ensure that coincidence detector
120
indicates that the signals are not coincident. Then, using the following sequence of steps, the spacing between the two edges is reduced incrementally until coincidence detector
120
Behiel Arthur J.
Cho James H
Tokar Michael
Xilinx , Inc.
Young Edel M.
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