Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-01-31
2002-06-25
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S167000
Reexamination Certificate
active
06412041
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a real time processing method of a flash memory, and more particularly to a real time processing method of a flash memory to effectively provide a simultaneous access to different banks as well as the same bank of the flash memory.
2. Description of the Prior Art
Flash memory, which Was developed by Intel corporation for the first time in the early 1980's is a type of EPROM which needs no additional hardware for a program. Further, data erase or write operation from or to the memory can be performed by software.
Since such flash memory is non-volatile and can be programed, in recent fews years. it is widely used as a program/data storage unit for mobile appliances such as mobile phones and PDAs.
Flash memory is classified into a single bank flash memory or a double bank flash memory according to its bank structure. In general, the single bank flash memory cannot perform two different operations at the same time, whereas the double bank flash memory can perform two different operations simultaneously since it has two banks each of which performs one operation. Therefore, the double bank flash memory can reduce access error and access time when compared to the single bank flash memory.
Here, access error means an error occurring when that data is not stored in the flash memory, even under a store command from an application program.
Further, in order to prevent access error, an access control is performed that does not permit more than two accesses simultaneously in the same bank. A central processing unit waits till an erase operation, with respect to a block, is finished because a read or a write (read/write) operation may not be performed, which is called an access delay.
FIG. 1
illustrates the structure of a single bank flash memory and a double bank flash memory in general. A block means an erasion block which is a unit that may be erased at once.
As shown in
FIG. 1A
, a single bank flash memory has several erasion blocks in a flash memory package. As shown in
FIG. 1B
, a double bank flash memory has two banks, each of which has several erasion blocks.
In the state that one operation is not completed in a block, a single bank flash memory cannot perform other operations in the block as well as in other blocks.
For example, as shown in
FIG. 1C
, while an erase operation is being performed with respect to the block of number
1
in a single bank flash memory, a write operation cannot be performed to the block of number
7
.
Further, in a double bank flash memory, while an operation is carried out in a bank, another operation can be performed in a different bank even though another operation cannot be carried out with respect to the same bank.
For example, as shown in
FIG. 1D
, while an erase operation is being carried out to the block of number
3
in the first bank, a write operation can be performed to the block of number
5
in the second bank so that the access error and the access delay can be reduced.
However, while the erase operation is being carried out to the block of number
3
in the first bank, a write operation cannot be performed to the block of number
2
in the first bank. That is, the write operation can only be performed after the erase operation is completed, and thereby lengthen the access delay time period.
In general, since a flash memory has an erase operation speed lower than a read and a write operation speed, the erase operation causes the access delay time to be lengthend.
For example, as shown in
FIG. 1D
, in order to update data in the block number
2
in the first bank, necessary steps are as follows.
FIG. 2
is a flow chart for explaining the operations of a general double bank flash memory. As shown in
FIG. 2
, if an access to a certain block of a double bank flash memory is requested in order to carry out a read/write operation (S
1
), a determination is made as to which bank of the first bank and the second bank has a block to which the access is requested (S
2
). A determination is made whether the access to the bank is possible, that is, whether a read, a write, or an erase operation is being carried out to the bank (S
3
).
At this time, if the access is impossible since a read, a write, or an erase operation is being carried out to the bank, the access is delayed until the access is possible with the read, write, or erase operation with respect to the bank completed (S
4
). After the read, write, or erase operation is completed, the read/write operation is performed by accessing the bank (S
5
).
At this time, if about one and a half second time period is necessary for data to be stored in one block of a flash memory through an application program, an access delay time period of one and a half seconds times the number of blocks to each of which an erase operation is to be performed is necessary for storing data in the several blocks.
As stated above, in a conventional flash memory, while an erase operation to a bank is being carried out, if a read or a write operation to the same block or to another block is to be performed, since the read or the write operation is performed after the erase operation completion, an access delay time period is lengthened.
SUMMARY OF THE INVENTION
Accordingly, in order to solve the above problem, it is an object of the present invention to provide a real time processing method of a flash memory effectively capable of supporting simultaneous accesses to different banks as well as to same bank in a flash memory.
In order to achieve the above object, the method according to the present invention comprises the steps of (1) determining whether an access to the flash memory is possible if an access to a block of the flash memory is requested in order to perform a read/write operation; (2) determining whether an erase operation is performed in the flash memory if the access to the flash memory is impossible in the step (1), and suspending the erase operation if the erase operation is being performed;
(3) performing the read/write operation by accessing the flash memory if the access to the flash memory is possible in the step (1) or if the erase operation in the flash memory is suspended in the step (2); and (4) resuming the erase operation which is suspended in the step (2) if the step (3) is finished.
Therefore, if an access to a block of a flash memory is requested for a read/write operation while an erase operation is performed with respect to a different block of the same memory, the erase operation is instantly suspended, the read/write operation is performed first, and then the erase operation is resumed, to thereby reduce an access delay and an access error. Therefore, a data read/write operation is processed in real time.
REFERENCES:
patent: 5509134 (1996-04-01), Fandrich et al.
patent: 6151657 (2000-11-01), Sun et al.
patent: 6189070 (2001-02-01), See et al.
patent: 6260103 (2001-07-01), Alexis et al.
patent: 6279070 (2001-08-01), Jeong et al.
patent: 6301635 (2001-10-01), Bothwell et al.
Portka Gary J.
Samsung Electronics Co,. Ltd.
Sughrue & Mion, PLLC
Yoo Do Hyun
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