Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-26
2002-08-06
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S167000, C438S933000
Reexamination Certificate
active
06429061
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to complementary metal oxide semiconductor (CMOS) device manufacturing, and in particular to a method of forming a strained Si CMOS structure wherein the strained Si channel layer of the structure is formed after conducting various high-temperature processing steps and after conducting various processing steps that typically consume Si.
BACKGROUND OF THE INVENTION
In the semiconductor industry, ‘strained Si on SiGe CMOS’ essentially refers to CMOS devices fabricated on a substrate that consists of a relatively thin (about 50 to about 300 Å) strained Si layer epitaxially grown on top of a relatively thick (about 300 to about 20,000 Å) relaxed SiGe layer. Publications in the past have shown the potential of achieving high-electron and hole mobilities in strained Si layers. More recent publications have experimentally demonstrated that strained Si layers can be used as a channel region for metal oxide field effect transistors (MOSFETs), and have shown that device performance is enhanced in these structures compared to devices fabricated on conventional Si substrates.
One of the difficulties in realizing strained Si CMOS technology is that the strained layer needs to be protected from high-temperature processing steps during the fabrication process. Exposure to high-temperature processing steps generally relaxes the strain in the strained layer. Moreover, ion implantation, which is typically used in well formation, may damage the strained Si layer degrading the device properties and diminishing the performance enhancements that can be advantageously obtained when using strained Si layers.
Furthermore, the thinner the strained layer is, the larger thermal stress the strained layer can withstand without noticeable device degradation. However, various processing steps including oxidation and etching (e.g., chemical etching and dry etching) consume the top Si layer; thus, in present processing of strained CMOS devices, the epitaxially strained Si layer has to be sufficiently thick to cover the potential thickness loss that may occur during oxidation and/or etching.
In view of the drawbacks mentioned hereinabove with prior art strained Si CMOS technology, there is a continued need to develop new and improved methods whereby the various prior art problems are substantially eliminated. That is, a method of providing a strained Si CMOS device is needed wherein the strained Si layer is formed after most of the high-temperature CMOS processing steps have been completed and after most of the processing steps that consume Si have been completed. Such a method would provide a higher performance device than heretofore possible with prior art strained Si CMOS devices.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a strained Si CMOS device wherein the strained Si layer is not adversely affected by high-thermal budget processing steps.
Another object of the present invention is to provide a strained Si CMOS device in which the strained Si layer is not consumed by processing steps that are known to consume Si in the active device areas, thereby minimizing the required thickness of the strained Si layer.
A further object of the present invention is to provide processing steps of fabricating a strained Si layer which are compatible with existing FET processing steps.
These and other objects and advantages can be achieved in the present invention by utilizing the inventive method wherein the strained Si layer is formed after most of the high-temperature processing steps and after the Si consuming processing steps have been completed.
Specifically, the inventive method comprises the steps of:
(a) forming a relaxed SiGe layer on a surface of a substrate;
(b) forming isolation regions and well implant regions in said relaxed SiGe layer; and
forming a strained Si layer on said relaxed SiGe layer.
In one embodiment of the present invention and prior to conducting step (b) above, an optional overlayer is formed on the relaxed SiGe layer. When an overlayer is present, the overlayer is typically removed prior to forming the strained Si layer and the strained Si layer is formed in the area previously occupied by the overlayer.
In the present invention, the strained Si layer may be formed by a selective epitaxial growth process wherein the strained Si layer is formed only in areas of the relaxed SiGe layer that are exposed. Alternatively, a non-selective epitaxial process may be used in forming the strained Si layer. If a non-selective epitaxial growth process is employed, the strained Si layer is formed over the entire structure, and lithography and etching are used to remove the strained Si layer from over the isolation regions
The inventive processing steps mentioned above may be used in conjunction with conventional gate processing steps including gate dielectric formation, gate stack formation, source/drain diffusion implantation, and etc. which are capable of forming a FET on the strained Si layer.
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Everhart Caridad
Rocchegiani Renzo N.
Schecter Manny W.
Scully Scott Murphy & Presser
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