Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-07-09
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S478000, C438S481000, C438S492000, C438S723000, C438S762000, C438S770000, C156S345420
Reexamination Certificate
active
06376387
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of and a system for sealing an epitaxial silicon layer formed on a semiconductor wafer.
2. Discussion of Related Art
Integrated circuits are formed in and on silicon and other semiconductor wafers. Wafers are made by extruding an ingot from a silicon bath and sawing the ingot into multiple wafers. In the case of silicon, the material of the wafers is monocrystalline. An epitaxial silicon layer is then formed on the monocrystalline material of the wafer. The epitaxial silicon layer is typically doped with boron and has a dopant concentration of about 1×10
16
atoms per centimeter cube. A typical epitaxial silicon layer is about five microns thick. The material of the epitaxial silicon layer has better controlled properties than the monocrystalline silicon for purposes of forming semiconductor devices therein and thereon.
Once the epitaxial silicon layer is formed, the wafer is removed from the wafer processing chamber and exposed to ambient air. The air oxidizes the exposed epitaxial silicon layer to form a native oxide layer thereon. The epitaxial silicon layer and the native oxide layer are exposed to contaminants in the air and are usually filled with impurities and particles. When semiconductor devices are formed on a surface which is filled with impurities, the electronic devices often fail.
It has been suggested that exposure of an epitaxial silicon layer to ozone gas will provide an efficient process for forming a very pure oxide layer on the epitaxial silicon layer.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. An epitaxial silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.
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Carlson David K
Comita Paul B.
Du Bois Dale R.
Riley Norma B.
Applied Materials Inc.
Blakely & Sokoloff, Taylor & Zafman
Bowers Charles
Sarkar Asok Kumar
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