Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-12-23

2002-09-03

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C719S323000

Reexamination Certificate

active

06446227

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a semiconductor memory device that is provided with a data compressing circuit that compresses and outputs read data, and shortens the time for testing.
2. Background Art
In order to shorten the testing time when testing semiconductor memory devices, it has been the conventional practice to simultaneously test several devices using an LSI tester. The number of measurement terminals on the LSI tester used in the test is limited, however. Accordingly, the number of semiconductor memory devices that can be simultaneously tested has been restricted based on the number of output terminals possessed by the semiconductor memory device.
For example, in the case of a semiconductor memory device having an 8 bit output terminal number, only 8 devices can be tested simultaneously in an LSI tester capable of simultaneously testing 64 terminals.
Similarly, in the case of a semiconductor memory device having a 16 bit output terminal number, only 4 devices can be tested simultaneously in an LSI tester capable of simultaneously testing 64 terminals.
At present, the bit number for data processing in microcomputers and the like is rising, however, so that an increase in the output terminal number beyond those cited above can be anticipated.
At the same time, advances in process technologies in the field of semiconductor manufacturing have led to an increase in the memory capacity per semiconductor memory device.
In particular, the holding characteristics for the charge held in the memory capacitor must be tested in the dynamic random access memory (DRAM). In this test, data is written into the memory cell, read out several seconds later for example, and a judgment is made as to whether or not the read out information is the same as the write information. Because this test is carried out for each semiconductor memory device, or for each memory cell, it requires several hours.
Thus, when the semiconductor memory device has an output terminal number of 64, the number of semiconductor memory devices which can be tested each time is just one in the case where using a LSI tester capable of simultaneously testing 64 terminals. While increasing the number of measurement terminals which can be tested simultaneously in the LSI tester might be considered, it becomes an extremely expensive capital investment in order to carry out high accuracy testing of properties at high speed.
Moreover, since it is not clear how many output terminals will be in future generations of semiconductor memory devices, it is impossible to determine how far the test bit number needs to be increased.
When testing a semiconductor memory device, a data compressing test mode is employed as a method for performing multiple bit testing simultaneously with a limited output terminal number. Namely, in a semiconductor memory device having a 16 bit output terminal number, 16 bit data is data compressed to 2 bits, and output from two output terminals. As a result, an LSI tester capable of simultaneously testing 64 terminals can test 32 semiconductor memory devices simultaneously without changing the testing time for each unit.
In a semiconductor memory device in which data from one or two input terminals typically determined in advance is input, if there is an input/output terminal number for the data in the semiconductor memory device—for example, 16 input/output terminals for a 16 bit data portion—then the same data is written in the memory cells for each 16 bits. When reading out the data stored in the memory cell, the 16 bit data values are compressed, and the value of the compressed result is used to determine whether or not the data is accurately stored in the memory cell. The above-described testing method is referred to a “parallel testing”.
For example, the means for carrying out the aforementioned data compression will be explained using
FIGS. 8
,
9
, and
10
.
FIGS. 8 and 9
are block diagrams showing the structure of data compressing circuit
100
in a semiconductor memory device having a conventional 16 bit (i.e., data terminal TD
0
~data terminal TD
15
) output terminal.
FIG. 10
is a schematic diagram showing the structure of a semiconductor memory device (DRAM: dynamic random access memory) in which the data compressing circuit shown in
FIGS. 8 and 9
is installed.
In
FIG. 10
, the memory cell domain is divided into four domains, i.e., memory bank BANK
100
~memory bank BANK
103
. Each of the memory banks is formed of four blocks. Memory bank BANK
100
~memory bank BANK
103
are formed in the same manner, and the operation enable state is selected according to an address signal input from an external device.
For this reason, memory bank BANK
100
will be explained in detail as a representative example of memory bank BANK
100
~memory bank BANK
103
. Structural components in the other memory banks which are identical to the structures in memory bank BANK
100
will be assigned the same numeric symbol and an explanation thereof will be omitted.
Memory bank BANK
100
is formed of memory block MB
100
~memory bank MB
103
. X decoder XDEC
100
activates a specific word line based on an address signal input from an external device. Y decoder YDEC
100
activates a column switch (Y switch) which connects a specific bit line to a global I/O line based on the address signal input from the external device.
Four global I/O lines GIO
100
~GIO
103
(corresponding to data terminal TD
0
~data terminal TD
3
, respectively) are provided to memory block MB
100
. Data amp DAP
100
~data amp DAP
103
are connected to global I/O line GIO
100
~global I/O line GIO
103
, respectively. Data amp DAP
100
~data amp DAP
103
increase the voltage of the data in the bit line selected by the column switch when reading out the data recorded in the memory cell of the semiconductor memory device during data read out.
Similarly, global I/O line GIO
104
~global I/O line GIO
107
(corresponding to data terminal TD
4
~data terminal TD
7
), global I/O line GIO
108
~global I/O line GIO
111
(corresponding to data terminal TD
8
~data terminal TD
11
), and global I/O line GIO
112
~global I/O line GIO
115
(corresponding to data terminal TD
12
~data terminal TD
15
) are provided to memory block MB
101
~memory block MB
103
, respectively.
Global I/O line GIO
104
~global I/O line GIO
107
, global I/O line GIO
108
~global I/O line GIO
111
, and global I/O line GIO
112
~global I/O line GIO
115
, are connected to data amp DAP
104
~data amp DAP
107
, data amp DAP
108
~data amp DAP
111
, and data amp DAP
112
~data amp DAP
115
, respectively.
For example, a specific memory cell in the memory block MB
100
shown in
FIG. 10
is selected by activating the word line corresponding to X decoder XDEC
100
and the column switch corresponding to Y decoder
100
, and the voltages of the data recorded in each of the memory cells is read out to global I/O line GIO
100
~global I/O line GIO
103
.
Data amp DAP
100
~data amp DAP
103
amplify the voltage corresponding to the data read out from each global I/O line GIO
100
~global I/O line GIO
103
(corresponding to data terminal TD
0
~data terminal TD
3
). As a result, data amp DAP
100
outputs data signal RWBST
100
and data signal RWBSN
100
, which is the inversion of data signal RWBST
100
, to line LT
100
and line LN
100
, respectively.
Data amp DAP
101
~data amp DAP
103
output data signal RWBST
101
~data signal RWBST
103
and data signal RWBSN
101
~data signal RWBSN
103
, obtained by inverting data signal RWBST
101
~data signal RWBST
103
, to line LT
101
~line LT
103
and line LN
101
~line LN
103
.
A specific memory cell in memory block MB
101
is selected by activating the word line corresponding to X decoder XDEC
100
and the column switch corresponding to Y decoder
100
, and the voltages of the data recorded in each of the memory cells are read out to global I/O line GIO
104
~global I/O line GIO
107
, respectively.
Data amp DAP
104
~data amp DAP
107
amplify the voltages corresponding to the data read out from each global I/O line GIO

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2911616