Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-13
2002-08-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C365S185180
Reexamination Certificate
active
06441443
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile memory structure and, more particularly, to a flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same.
BACKGROUND OF THE INVENTION
Flash memories have been widely used in small electronic products such as notebook computers or digital cameras. Moreover, along with the trend of miniaturization of electronic products, the sizes of flash memories need to be smaller and smaller. However, when small-size flash memories are manufactured by means of sub-micrometer fabrication technology, the transistors of memory cells in the memory cell array must be operated at a small voltage about 3V because of short channel effects.
FIG. 1
shows a memory cell structure of a prior art flash memory. N-type doped-regions used as a source
12
and a drain
14
are formed in a p-type semiconductor substrate
10
, and a channel is formed in the substrate
10
between the source
12
and drain
14
. A silicon dioxide layer
16
, a trapping layer
18
(e.g., silicon nitride), and a silicon dioxide layer
20
are formed in turn on the surface of the substrate
10
. A control gate
22
is then formed on the surface of the silicon dioxide layer
20
. When a programming process is performed to the memory cell, a sufficiently large voltage must be applied to the drain and the source so that the above action can be accomplished by means of the channel formed by this high voltage difference. Therefore, the operational voltage of a prior art flash memory cannot be easily reduced so that the operational voltage is too high. Moreover, the structure of the memory cell array is required to be denser and denser so that the channel length is reduced therewith, resulting in mutual influence of operation between each memory cell. If the operational voltage cannot be relatively reduced, short channel effects will arise so that the phenomenon of punch through will occur. Furthermore, because complex design of peripheral circuits is required for higher operational voltages, the above high-voltage operational method will complicate the design of peripheral circuits.
The simplest way to resolve the above short channel effects is to reduce the operational voltage or to change the operational mode to facilitate the miniaturization of memory cell. Accordingly, the present invention proposes an improved structure of flash memory cell and a method for operating the same to resolve the above problems in the prior art.
SUMMARY OF THE INVENTION
The primary object of the present invention is to provide an improved structure of flash memory cell and a method for operating the same. A shallow doped-region is added below the doped-region used as the drain. Using these two different doped-regions to share the voltage, the voltage can be controlled and the operational voltage of the memory cell can be reduced. Moreover, the design of peripheral circuits will be simpler.
Another object of the present invention is to provide an embedded type flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same.
According to the present invention, an n-well is formed in a p-type substrate. A shallow p-well is formed in the n-well, and a drain and a source of shallower n-type doped-regions are formed in the shallow p-well and the n-well, respectively. A dielectric insulating layer and a poly-silicon gate are stacked above the n-well to connect all the drains.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:
REFERENCES:
patent: 5677215 (1997-10-01), Goo
patent: 5751631 (1998-05-01), Liu et al.
patent: 5956271 (1999-09-01), Kaya
patent: 5999443 (1999-12-01), Ling et al.
patent: 6091101 (2000-07-01), Wang
patent: 6232183 (2001-05-01), Chen et al.
patent: 6262914 (2001-07-01), Smayling et al.
Hsu Ching-Hsiang
Yang Ching-Sung
Ememory Technology Inc.
Ho Tu-Tu
Nelms David
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