Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-27
2002-09-24
Callahan, Timothy P. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06457161
ABSTRACT:
The present invention relates to a method and a computer program product for modeling a latch-based design logic circuits to enable the use of conventional circuit analysis software programs.
BACKGROUND OF THE INVENTION
Sugisawa et al U.S. Pat. No. 5,619,511 granted on Apr. 8, 1997 for “Dynamic Scan Circuit and Method of Using Same”, Fetherston et al in “Testability Features of AMD-K6 Microprocessor”, International Test Conference 1997, pp. 408-413, both incorporated herein by reference, and
FIG. 1
herein show examples of latches that need to be modeled in order to enable several circuit analysis software programs like Automatic Test Pattern Generator (ATPG), fault simulator, testability analysis, and others to handle this type of circuit. These software programs usually assume that the memory elements used in the circuit are D-type edge-triggered flip-flops. A D-type edge-triggered flip-flop actually contains two latches connected in series. That is, a first latch captures the data input of the flip-flop, and the output of this first latch is connected to the input of the second latch. Finally, the output of the second latch also constitutes the output of the edge-triggered flip-flop. The clock of the two latches is derived from the same input clock. The input clock to the edge-triggered flip-flop is connected to the clock input of the second latch whereas the clock input of the first latch is connected to the inverse of the input clock. This way, the two latches are never transparent at the same time.
Banik et al U.S. Pat. No. 5,742,190 granted on Apr. 21, 1998 for “Method and Apparatus for Clocking Latches in a System Having Both Pulse Latches and Two-Phase Latches”, incorporated herein by reference, illustrates an example of a circuit being addressed herein. The circuit has a combination of latches clocked by a first and second clock phase as well as by a pulse derived from the second clock phase. The latches which are clocked by such pulse are referred to as pulse latches. The patent describes a method of generating clock pulses from the second clock phase. A pulse latch behaves almost exactly like an edge-triggered flip-flop because the latch updates its output and captures its input around the time of the rising edge of the second clock phase. The difference is that the capture occurs on the falling edge of the pulse. The width of the pulse can be made very small so that a pulse latch can be treated like an edge-triggered flip-flop for the purpose of circuit analysis. Most software programs of the type mentioned earlier cannot handle circuitry of this type.
Parvathala et al U.S. Pat. No. 5,872,785 granted on Feb. 16, 1999 for “Method and Apparatus for Scan Testing of Multi-Phase Logic”, incorporated herein by reference, describes a circuit modeling technique for latch-based circuits. However, there is a number of limitations with this technique. First, the method does not show how to model the scan cells. These cells are not readily recognizable by the software programs assuming edge-triggered flip-flops. Second, the patent does not describe how to model latches associated with the second clock phase that also use a non-scan cell which are common in high-performance circuits. Third, the patent does not describe how to model pulse generators found in circuits containing pulse latches. Fourth, the patent does not describe how to validate the underlying assumptions under which the models can be used.
In order to overcome these problems, it has been necessary to modify or model portions of a circuit description in such a manner as to allow existing software programs to operate properly. Heretofore, this has been a time consuming, manual task. It would be desirable to provide a method and program product for automating the modeling of circuits of complex latch-based designs of the type described above.
SUMMARY OF THE INVENTION
One aspect of the present invention is defined as a method of modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of the latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when the latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of the latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch.
Another aspect of the present invention relates to a computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of the latches being scannable, the computer program product comprises, a computer readable storage medium; means recorded on the medium for, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; means recorded on the medium for modeling the latch as a buffer connected between the data input and output of the latch when the latch is associated with the first clock phase, and means recorded on the medium for modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch when the latch is associated with the second clock phase.
REFERENCES:
patent: 3783254 (1974-01-01), Eichelberger
patent: 5619511 (1997-04-01), Sugisawa et al.
patent: 5742190 (1998-04-01), Banik et al.
patent: 5872795 (1999-02-01), Parvathala et al.
patent: 6247154 (2001-06-01), Bushnell et al.
patent: 6247165 (2001-06-01), Wohl et al.
E.B. Eichelberger et al, “Logic Design Structure for LSI Testability”, The Proceedings of the 14th Design Automation Conference, 1977, pp. 462-468.
Burek Dwayne
Maamari Fadi
Nadeau-Dostie Benoit
Callahan Timothy P.
Cox Cassandra
Proulx Eugene E.
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