Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-09-03
2002-05-07
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S778000, C438S786000, C438S787000
Reexamination Certificate
active
06383951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to materials for use with integrated circuits and methods of making the same, and in particular to insulating materials having low dielectric constants for electrical isolation in high density integrated circuits.
2. Description of the Related Art
When fabricating integrated circuits (ICs), layers of insulating, conducting and semiconducting materials are deposited and patterned in sequence. The lowest levels or layers in the IC form electrical devices, such as transistors, separated by field isolation elements, with gate electrodes protected by insulating spacers. Memory cell capacitors are also associated with the lower layers for certain circuits. These electrical devices are generally interconnected by patterned wiring layers and interlevel contacts formed above the devices.
Conductive elements, like the transistor active areas and gates, capacitors, contacts and wiring layers, must each be electrically isolated from one another for proper circuit operation. The field isolation elements (e.g., field oxide) and gate spacers contribute to the isolation of transistor elements. Higher wiring layers include insulating material between the wiring layers, as well as between metal lines or runners within a wiring layer. Such insulating layers are often referred to as interlevel dielectrics (ILDs).
Continued miniaturization of ICs results in, among other things, shortened spacing between adjacent lines. Scaling the space between lines leads to increased parasitic capacitance, which delays signal transmissions. The delayed signal transmission thwarts the pursuit of higher operating speeds and lower power consumption, the very features which the scaling is designed to accomplish. Similarly, thinner isolation among electrical devices in the lower layers also exhibits parasitic capacitance as dimensions are scaled down.
IC operating speed can be enhanced by reducing the parasitic capacitance between the metal lines. As a general proposition, one way to reduce capacitance is to use a material with a low dielectric constant (k). Known processes to manufacture low k material, however, are unsatisfactory as they insufficiently lower the dielectric constant (relative to conventional oxides, for example) or cause difficulty when integrated with other necessary or desirable fabrication processes.
Accordingly, there is a need for improved processes providing material having a low dielectric constant. Desirably, such processes should be compatible with conventional fabrication techniques, and thereby easily integrated with existing technology.
SUMMARY OF THE INVENTION
The present invention satisfies these needs by providing materials having low dielectric constants for electrically isolating insulating material in ICs, and methods of manufacturing the same. Advantageously, the material can be formed with a low dielectric constant without the need for a cap layer.
In accordance with one aspect of the invention, a method for providing electrical isolation between conductive elements in an integrated circuit, includes the provision of a substrate with a partially fabricated integrated circuit. An organosilane gas source is reacted with an oxidizing agent to form a layer over the substrate. The layer is predominantly formed of silicon hydroxide and incorporates carbon. This layer is then plasma treated without forming a layer during the plasma treatment. The treatment converts the silicon hydroxide layer to an insulating material having a lower dielectric constant.
In accordance with another aspect of the invention, a process is disclosed for forming a low dielectric constant material. An organosilane gas is reacted to form a first material on a substrate. The first material is then exposed to a plasma which contains oxygen in order to convert the first material to a second material without forming a layer over the first material. The second material has a dielectric constant of less than about 3.5.
In accordance with another aspect of the invention, a process for forming a low dielectric material includes forming a layer of silicon hydroxide which incorporates carbon. This layer is then annealed at a temperature of at least about 500° C.
In accordance with another aspect of the invention, an insulating material is provided between conductive elements in an integrated circuit. The material includes a polysiloxane network incorporating carbon-silicon bonding, and exhibits a dielectric constant of less than about 3.3.
In accordance with another aspect of the invention, an integrated circuit is provided. The circuit includes first and second conductive elements, which provide first and second electrical paths of the circuit, respectively. A unitary insulating layer directly contacts and is sandwiched between the first and second conductive elements. The insulating layer includes polysiloxane incorporating carbon, and has a dielectric constant of less than about 3.5.
This process drives off water to leave a polysiloxane network incorporating carbon. Advantageously, the material exhibits a low dielectric constant while the process is easily integrated with a variety of IC fabrication processes.
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Brophy Jamie L.
Jr. Carl Whitehead
Knobbe Martens Olson & Bear
Micro)n Technology, Inc.
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