Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-25
2002-09-24
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000, C438S981000
Reexamination Certificate
active
06455378
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device manufacturing method and a semiconductor device. Particularly, the present invention relates to a technology that is effectively applicable to a semiconductor device having a trench-gate structured power field-effect transistor (hereafter simply referred to as the trench power transistor).
BACKGROUND OF THE INVENTION
The inventors have examined the following manufacturing technology for trench power transistor. On a principal plane of a semiconductor substrate, there is formed a trench extending in a direction which crosses the principal plane. A gate oxidation treatment is then applied to the semiconductor substrate to form a gate oxidation film on an inner wall face (bottom and side surfaces) of the trench. Subsequently, say a polycrystal silicon film is deposited on the principal plane of the semiconductor substrate by preventing the polycrystal silicon film from filling the trench. Then, a gate electrode is formed by etching back the polycrystal silicon film so that the polycrystal silicon film remains in the trench.
Generally, thinning a gate insulator improves the power field-effect transistor's drive capability. However, excessively thinning the gate insulator of the trench power transistor also thins the film thickness at the bottom, failing to ensure a pressure resistance. Doing so also increases a capacity between a gate and a drain, thus increasing a switching loss for the trench power transistor. Accordingly, the above-mentioned technology needs to relatively thicken the gate insulator all over the inner wall face of a trench so that these problems should not occur. This also causes a problem of impeding improvement of the trench power transistor's drive capability. For example, Japanese Patent Laid-Open Publication No. 1-192174 documents the technology for preventing a decrease in the gate pressure resistance at the trench bottom of a trench power transistor. The publication discloses the structure in which the insulator thickness at the trench bottom is thicker than that on the trench's side face.
SUMMARY OF THE INVENTION
However, the inventors found the following problems in the technology disclosed in the above-mentioned publication.
According to the technology disclosed in the abovementioned publication, a source-drain region of a trench power transistor is formed on a semiconductor substrate. Then, the semiconductor substrate is trenched and processed with the gate oxidation treatment. Therefore, there is a problem that impurities in the source-drain drain region may diffuse during heat treatment or the like to follow using the silicon nitride film as an oxidation-resistant mask. It is difficult to form a shallow junction in the source region. As it is difficult to set and control a channel length for the trench power transistor, there arises a problem of degrading the trench power transistor performance.
A general object of the present invention is to provide a technology which can decrease a capacity between the gate and drain in the trench power transistor.
It is a more specific object of the present invention to provide a technology which can improve the trench power transistor's drive capability.
It is another object of the present invention to provide a technology which can improve the gate insulation pressure resistance of the trench power transistor.
It is still another object of the present invention to provide a technology which can form a shallow junction for the source region in the trench power transistor.
It is a further object of the present invention to provide a technology which can improve controllability of the source region and the channel region in the trench power transistor.
It is a still further object of the present invention to provide a technology which can improve the trench power transistor performance.
Other objects and new features of the present invention will become apparent from the detailed description in this specification to follow taken in conjunction with the accompanying drawings.
The present invention disclosed in this specification is broadly summarized as follows.
That is, according to the present invention, a gate insulator is formed in a trench on a semiconductor substrate so that the trench bottom becomes relatively thicker than the trench's side face. Then, a gate is formed in the trench. Further, the semiconductor substrate is provided with impurities for forming a semiconductor region of the field-effect transistor.
During a manufacturing process of the semiconductor substrate, the present invention has a step of forming an epitaxial layer containing second impurities on the surface of the semiconductor base substance containing first impurities so that the density of the second impurities becomes smaller than that of the first impurities.
According to the present invention, an impurity density for the gate is greater than impurity densities for the channel region and a source region.
The present invention has a step of forming a first insulator on a principal plane of the semiconductor substrate, then removing a region where the trench is formed from the first insulator to form an opening, and then planing the semiconductor substrate exposed from the opening by using the first insulator as a mask to form the trench.
The present invention has a step of rounding corners of the trench bottom.
The present invention has a step of making the first insulator's opening larger than the trench size after the step of forming the trench and before the step of forming the gate insulator.
In the present invention,
the step of forming the gate insulator comprises the steps of:
forming a second insulator on an inner face of the trench;
forming an oxidation-resistant third insulator on the second insulator surface;
etching back the third insulator to leave it on the trench side face;
applying oxidation treatment to the semiconductor substrate to selectively form a relatively thick insulator on a region exposed from the third insulator on the semiconductor substrate;
removing the third insulator, then removing the second insulator; and
applying oxidation treatment to the semiconductor substrate after removing the second insulator to form a gate insulator which provides a greater thickness on the principal plane of the semiconductor substrate exposed from the opening in the first insulator and the trench bottom than on the trench side face.
The step of forming the gate further comprises of the steps of:
depositing a conductor film in the trench and on the principal plane of the semiconductor substrate; and
etching back the conductor film to form the gate whose cross section is T-shaped.
After the oxidation treatment is used to form a gate insulator, the present invention has a step of depositing an insulator through the use of chemical vapor growth on the surface of the gate insulator.
According to the present invention, a gate insulator is formed in a trench on the semiconductor substrate so that a trench bottom and a trench shoulder become thicker than a trench side face. A gate is formed so that it is embedded in the trench and is extended on the semiconductor substrate's principal plane. A field-effect transistor's semiconductor region is formed on the semiconductor substrate.
REFERENCES:
patent: 4992390 (1991-02-01), Chang
patent: 5473176 (1995-12-01), Kakumoto
patent: 6198127 (2001-03-01), Kocon
patent: 1-192174 (1989-08-01), None
Inagawa Hiroshi
Machida Nobuo
Oishi Kentaro
Chaudhari Chandra
Hitachi , Ltd.
Mattingly, Stanger & Malur
LandOfFree
Method of manufacturing a trench gate power transistor with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a trench gate power transistor with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a trench gate power transistor with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2901047