Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-09-16
2002-05-28
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S713000, C438S714000
Reexamination Certificate
active
06395639
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuit devices, most generally, and the processes for forming these devices. More specifically, this invention relates to the materials, processes, and structures used to provide a pattern within a gate electrode film including both isolated and tightly packed features having the same dimensions.
BACKGROUND OF THE INVENTION
At critical levels in integrated circuit device manufacturing, the control of critical feature dimensions and the etching processes which determine critical feature dimensions, become increasingly important as device features continue to shrink in size. An example of a critical feature dimension is line width. Line width control is especially important in the formation of gate electrodes of transistors formed within a semiconductor substrate. Gate electrode structures are formed by first forming a semiconductor film on a semiconductor substrate, then patterning the semiconductor film. By “patterning”, it is meant that a film is formed, then portions of the film are removed by etching or other methods. The portions of the original film which remain, constitute the “patterned” film.
As gate electrode dimensions continue to shrink, it has become increasingly more important to accurately and repeatably pattern the gate electrode film to produce features having desired and predictable dimensions. It has also become more important to develop the ability to pattern the film in such a manner as to produce both isolated and tightly-packed features having the same dimensions. As such, the use of a “hardmask” has been widely adopted for forming a pattern within the gate electrode film.
A hardmask is a dielectric film such as a silicon nitride film, an oxide film, or a silicon oxynitride film which is formed over the gate electrode film prior to patterning the gate electrode film. An anti-reflective coating may additionally be formed over the dielectric film to aid in patterning. The anti-reflective coating may be a spun-on polymeric film such as an organic film, or it may be an anti-reflective film formed by other means such as by chemical vapor deposition. A pattern is first formed within a masking material such as photoresist over the hardmask material. The hardmask is then etched, transferring the pattern from the masking material to the hardmask material. After the masking material has been removed, the hardmask material serves as a masking medium and the pattern formed in the hardmask film is then transferred to the gate electrode film, typically by means of etching. It has been found that the dimensions of the hardmask pattern are transferred quite accurately to the corresponding features of the gate electrode film during the gate electrode etching process which uses the hardmask pattern as a mask. It has also been found that the hardmask etch, which transfers the pattern of the photoresist masking material to the hardmask, is the largest contributor to variation in the final dimensions of the features formed within the gate electrode film, such as the gate length of a gate electrode serving as part of a transistor formed within the semiconductor substrate. As such, there is a demonstrated need to predictably, accurately, and repeatedly form features within a hardmask film having a desired dimension, from a pattern formed within a masking film produced according to the available technology.
In conventional hardmask etch processes, fluorinated gasses such as mixtures of CHF
3
and CF
4
have been used to etch the dielectric films which constitute the hardmask layer. Etch processes using these CHF
3
/CF
4
mixtures are effective in transferring the features formed in photoresist masking film patterns, to the hardmask film, for technologies where the features formed in the photoresist masking pattern, such as line width, have dimensions of 0.35 microns and greater.
As device sizes continue to shrink, it has become desirable to produce both isolated and tightly-packed features within the gate electrode film having dimensions less than 0.35 microns. In order to produce a patterned gate electrode film including both isolated and tightly-packed features having the same dimensions, it is also desirable to simultaneously produce both isolated and tightly-packed features within the hardmask film having the same dimensions, during a single etching process. Tightly-packed, or nested features will hereinafter simply be referred to as nested features.
Etch bias is the difference in the dimensions of an etched feature compared to the dimensions of a corresponding feature within the masking pattern, from which the etched feature is formed. As smaller and smaller features are being produced, localized etching effects have a greater influence upon the feature produced by etching. It becomes more difficult, at smaller dimensions, to maintain the same etch bias for isolated features and tightly packed or nested features formed during the same etching process. This is due to polymers which form on the sidewalls of the features being etched, during, and as a result of, the conventional etch processes used. An isolated feature accumulates more polymer buildup than one which is nested, or close to another feature—i.e., tightly-packed. The result of this phenomenon is that an isolated feature will have a larger final size than a nested feature formed simultaneously during the same etch process, even if the corresponding features of the photoresist masking film from which they are formed, are of the same dimension. At design rules of 0.35 microns or smaller, the difference in etch bias and therefore the difference in etched dimensions, between nested and isolated features, becomes unacceptably significant.
The etched features of the patterned gate electrode film include gate electrodes for transistors formed within the semiconductor substrate. The line width of a line formed within a patterned gate electrode film is the primary influence upon the effective gate length L
eff
of such a transistor and is dependant upon the line width of the corresponding line formed in the hardmask film which, in turn, is dependant upon the line width of the corresponding line formed in the masking film. Transistors having different gate lengths (L
eff
have different electrical properties. When transistors which are intended to have similar electrical properties, are formed having different electrical properties, device performance is degraded and overall yield is therefore decreased. The L
eff
of transistors formed within a semiconductor device must lie within a tight range for the devices to perform according to the desired set of operational characteristics. This becomes increasingly more important as technology allows for the production of smaller and smaller device features.
As such, it can be seen that a process which provides the same etch bias for both isolated and nested features, is desirable in the art.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention addresses the shortcomings of conventional attempts to produce nested and isolated features having the same dimensions within a hardmask film, and then within a gate electrode film. The present invention provides a hardmask etching process having substantially the same etch bias for isolated and nested features. Stated alternatively, the present invention provides a process for translating a pattern formed in a photoresist masking film, into a hardmask film without localized etching effects producing a difference in the dimensions of an isolated feature, compared to a nested feature, formed during the same process.
The present invention provides a process sequence including an argon treatment step followed by a C
2
F
6
etching step for etching the hardmask. The etch sequence is a robust sequence, resistant to localized etching effects such as polymer buildup during the etch process, and therefore allows for the formation of features of the same dimensions from photomask features having the same dimensions, re
Esry Thomas Craig
Layadi Nace
Luque Sylvia Marci
Molloy Simon John
Pita Mario
Agere Systems Guardian Corporation
Christie Parker & Hale LLP
Hiteshew Felisa
Vinh Lan
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