Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2000-10-24
2002-05-07
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S093000, C326S086000
Reexamination Certificate
active
06384635
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Japanese Patent Application No. 11-306174, filed Oct. 29, 1999, the entire disclosure of which is incorporated herein of reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a signal transmitting circuit having an input node for performing a predetermined process on a signal corresponding to an input signal which is input at an input terminal, specifically from an external device, and for transmitting the processed signal to an internal circuit.
2. Description of the Related Art
Semiconductor integrated circuits (hereinafter “ICs”), are widely used in electronic devices, such as a personal computer. Such ICs receive a signal from an external above-ranking device or from another device incorporated in the electronic device together with the IC, and performs predetermined processes on the signal.
The ICs described above are prepared to synchronize the input signal to be input with a several kinds of circuits incorporated in the ICs, and to operates a particular circuit incorporated in the ICs based on the input signal. To do so, the IC includes a signal transmitting circuit for performing processes to the input signal, for example, a process for delaying the input signal for a predetermined time or a process for generating a pulse signal having a particular pulse width in response to the input signal.
Typical signal transmitting circuits, which are commonly used in the several circuits, are shown in
FIGS. 12 and 13
. One signal transmitting circuit
10
, shown in
FIG. 12
, has a delay function and another signal transmitting circuit
15
, shown in
FIG. 13
, has a pulse generating function.
Referring to
FIG. 12
, the signal transmitting circuit
10
includes a two-input NAND gate
11
and a delay circuit
13
. The delay circuit
13
includes an even number of inverters
13
-
1
. . .
13
-k, which are connected in series. The input of the first inverter
13
-
1
of the delay circuit
13
is connected to an input terminal
1
for receiving an input signal. One of the two inputs of the NAND gate
11
is connected to the input terminal
1
, and another input of the NAND gate
11
is connected to the output of the last inverter
13
-k of the delay circuit
13
. An output terminal
3
is connected to the output of the NAND gate
11
. The output terminal
3
is connected to other circuits incorporated in the IC which utilizes the output signal from the output terminal
3
.
The operation of the signal transmitting circuit
10
is explained below with reference to FIG.
14
. In
FIG. 14
, a waveform referring to IN shows a voltage level of an input signal at the input terminal
1
shown in
FIG. 12. A
waveform referring to A shows a voltage level at the output of the last inverter
13
-k shown in
FIG. 12. A
waveform referring to OUT shows a voltage level of the output signal from the NAND gate
11
shown in FIG.
12
.
In the initial state of the signal transmitting circuit
10
, the input signal IN having a power supply voltage level (hereinafter “H level”), is input at the input terminal
1
. Since the voltage at the output of the last inverter
13
-k is at the H level, the voltage of the output signal OUT is maintained at a ground level (hereinafter “L level”). For purpose of illustration only, the power supply voltage and the ground voltage are assumed to be five volts (5V) and zero volt (0V), respectively.
At a time t
0
, when the voltage of the input signal IN, is changed from the H level to the L level, the voltage at the output of the last inverter
13
-k is maintained at the L level for a certain time period defined by the number of the inverters
13
-
1
. . .
13
k, because the input signal IN being input to the delay circuit
13
is delayed by the inverters
13
-
1
. . .
13
-k. As a result, the voltage of the output signal OUT is changed to the H level. Then, while the voltage at the output of the last inverter
13
-k is changed to the L level, the voltage of the output signal OUT is maintained at the H level.
Assuming that the voltage of the input signal IN is changed to the H level before the time t
1
, the voltage of the output signal OUT is maintained at the H level because the voltage at the output of the last inverter
13
-k is maintained at the L level by delaying the transmittance of the input signal IN. Assuming that the voltage at the output of the last inverter
13
-k is changed to the H level, the voltage of the output signal OUT is changed to the L level because the voltages of signals being input to the NAND gate
11
are at the H levels at this moment.
Therefore, the signal transmitting circuit
10
shown in
FIG. 12
provides a function for maintaining the voltage of the output signal OUT at the H level during the time period between the time when the voltage level is changed to the H level form the L level and the time t
1
corresponding to the delayed time delayed by the delay circuit
13
.
Next, the signal transmitting circuit
15
having the pulse generating function is explained with reference to the FIG.
13
. In
FIG. 13
, the same reference numbers as used in
FIG. 12
designate the same components. Referring to
FIG. 13
, the signal transmitting circuit
15
includes a two-input NAND gate
11
and the delay circuit
17
. The delay circuit
17
includes an odd number of inverters
17
-
1
. . .
17
-(k+1), which are connected in series. The input of the first invert
17
-
1
of the delay circuit
17
is connected to an input terminal
1
for receiving an input signal. One of the input of the NAND gate
11
is connected to the input terminal
1
, and another input of the NAND gate
11
is connected to the output of the last inverter
17
-(k+1) of the delay circuit. An output terminal
3
is connected to the output of the NAND gate
11
. The output terminal
3
is connected to other circuits incorporated in the IC, which utilizes the output signal from the output terminal
3
. Namely, the only deference is that the delay circuit
17
of the signal transmitting circuit
15
shown in
FIG. 13
includes the odd number of inverters while the delay circuit
13
of the signal transmitting circuit
10
shown in
FIG. 12
includes the even number of inverters.
The operation of the signal transmitting circuit
15
is explained below with reference to FIG.
15
. In
FIG. 15
, a waveform referring to B shows a voltage level on an output of the last inverter
17
-(k+1) shown in FIG.
13
. In the initial state of the signal transmitting circuit
15
, the input signal IN, having the H level is input at the input terminal
1
. Since the voltage at the output of the last inverter
17
-(k+1) shows at the L level, the voltage of the output signal OUT is maintained at the H level.
At a time t
0
, when the voltage level of the input signal IN is changed from the H level to the L level, the voltage at the output of the last inverter
17
-(k+1) is maintained at the L level for a certain time period defined by the number of the inverters, because the input signal IN being input to the delay circuit
17
is delayed by the inverters
17
-
1
. . .
17
-(k+1). As a result, the voltage of the output signal OUT is maintained at the H level. Then, while the voltage at the output of the last inverter
17
-(k+1) is changed to the H level, the voltage of the output signal OUT is maintained at the H level. Then, while the voltage at the output of the last inverter
17
-(k+1) is changed to the L level, the voltage of the output signal OUT is maintained at the H level.
Assuming that the voltage of the input signal IN is changed to the H level before the time t
1
, the voltage of the output signal OUT is changed to the L level because the voltages of signals being input to the NAND gate
11
are at the H levels at this moment. Assuming that the voltage at the output of the last inverter
17
-(k+1) is changed to the L level, the voltage of the output signal OUT is changed to the H level because one of the voltages o
Mimura Junichi
Oki Electric Industry Co. Ltd.
Tokar Michael
Tran Anh
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