Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-11-02
2002-05-21
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S190000, C365S227000, C365S228000, C365S226000, C365S196000, C365S051000, C365S189090, C327S057000, C327S051000
Reexamination Certificate
active
06392944
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device including a sense amplifier that senses and amplifies potential differences between paired bit lines. Particularly, the invention relates to a sense power supply structure for stably driving a sense amplifier even under a low supply voltage condition.
2. Description of the Background Art
With advances in integration degree of semiconductor memory devices, there arise the problems such as increase in power consumption, and reduction in break down voltage characteristics of the components due to miniaturization. To overcome these problems, a method of reducing an operational power voltage has been developed. For example, an insulating film forming a capacitor of a memory cell in a dynamic random access memory (DRAM) is miniaturized to be a significantly thin film. In view of reliability, potential difference to be applied across the insulating film needs to be reduced, and the method to reduce the operational power voltage is adopted as a countermeasure against such situation. Recently, the reduction in operational power voltage is remarkably progressed. On the other hand, the reduction in the operational power voltage is in a reverse technical direction in view of improvement in the operational characteristics such as sensing operation margin and speed.
FIG. 1
is a circuit diagram of a conventional semiconductor memory device, and particularly shows a configuration of a DRAM memory array. In the memory array, memory cells MC are arranged in rows and columns, word lines WL are disposed corresponding to respective rows of the memory cells MC, and the pairs of bit lines BL and ZBL are disposed corresponding to the respective columns of the memory cells MC.
FIG. 1
depicts a configuration of a portion related to a single pair of bit lines BL and ZBL.
The memory cell MC includes a capacitor CM for storing data and an access transistor TRM for connecting the capacitor to the bit line BL in response to a potential on the corresponding word line WL. The access transistor TRM is formed of an n-channel MOS (insulated gate type field effect) transistor. The memory cell capacitor CM receives a predetermined cell-plate voltage Vcp on one electrode node (cell plate node), and stores charge corresponding to stored data on the other electrode SN (storage node). The memory cell MC is connected to one of the corresponding bit lines BL and ZBL, and is shown to be connected to the bit line BL in FIG.
1
.
Corresponding to the pair of bit lines BL and ZBL, a sense amplifier SA and an bit-line equalize circuit EQ are provided. The sense amplifier SA senses and amplifies memory cell data. The bit line equalize circuit EQ precharges and equalizes the bit lines BL and ZBL to a predetermined potential in a standby state.
The sense amplifier SA includes cross-coupled p-channel MOS transistors SAP
1
and SAP
2
(sense transistors), and cross-coupled n-channel MOS transistors SAN
1
and SAN
2
. The sense amplifier SA senses and amplifies a potential difference generated between the bit lines BL and ZBL when made active.
The sense transistor SAP
1
is connected between the bit line BL and a node NP, and has the gate connected to the bit line ZBL. The sense transistor SAP
2
is connected between the bit line ZBL and the node NP, and its gate is connected to the bit line BL. The sense transistor SAN
1
is connected between the bit line BL and a node NN, and its gate is connected to the bit line ZBL. The sense transistor SAN
2
is connected between the bit line ZBL and the node NN, and its gate is connected to the bit line BL.
The sense amplifier SA is activated when a sense amplifier driving p-channel MOS transistor SDP and a sense amplifier driving n-channel MOS transistor SDN are each made conductive. The sense amplifier driving n-channel MOS transistor SDN is rendered conductive, in response to activation of a sense amplifier activating signal S
0
N, to electrically connect the source node NN of the sense transistors SAN
1
and SAN
2
to a sense power feed line VSL that feeds a ground potential GND. The sense amplifier driving transistor SDP is made conductive in response to activation of a sense amplifier activating signal ZS
0
P, and electrically connects the source node NP of the sense p-channel MOS transistors SAP
1
and SAP
2
to a power feed line VSH for transmitting a memory array power supply potential Vdds when made conductive.
A circuit formed including the sense amplifier SA, sense amplifier driving transistor SDN, and sense amplifier driving transistor SDP is hereinbelow referred to as a “sense amplifier/drive circuit SAD”.
The bit line equalize circuit EQ precharges and equalizes the bit lines BL and ZBL to an equalization potential Vbl according to an equalizing signal on an equalizing signal line BLEQ. The bit line equalize circuit includes a precharging transistor for transmitting the equalization potential Vbl to the bit lines, and an equalizing transistor for electrically short-circuiting the bit lines BL and ZBL with each other.
The power feed line VSH, which feeds the sense power voltage Vdds (memory array power supply potential), is connected to an internal voltage down converting circuit VDC. The voltage down converting circuit VDC down-converts an external power potential extVdd, and provides a sense amplifier driving power source at the memory array power potential Vdds.
FIG. 2
is a timing chart representing the operation of the sense amplifier SA shown in FIG.
1
. Before a time T
01
, specifically, before the word line WL is selected to rise in potential, both the bit line BL and bit line ZBL are precharged to a precharge or equalization potential Vbl. Here, the precharge potential Vbl is assumed to be Vdds/
2
, or the intermediate potential of the memory array power potential Vdds and the ground potential GND. Also, the memory cell MC is assumed to store H data (logical high level data).
At time T
01
, the word line WL rises in potential, the H data stored in the memory cell MC is read out onto the bit line BL, and a very small potential difference dV is produced between the bit lines BL and ZBL.
At time T
02
, the levels of the sense amplifier activating signals S
0
N and ZS
0
P become H and L levels, respectively; and the sense amplifier SA is activated. Through a sensing operation of the sense amplifier SA, the very small potential difference dV caused between the bit lines BL and ZBL is sensed and amplified. In this operation, since the access transistor TRM in the memory cell MC is conductive, the potential Vdds of the higher potential power feed line VSH is applied through the bit line BL and the transistor TRM to the storage node SN, which is one electrode of the capacitor CM in the memory cell MC.
Here, a threshold voltage of each of the n-channel MOS transistors SAN
1
and SAN
2
is represented by Vthn, and a threshold voltage of each of the p-channel MOS transistors SAP
1
and SAP
2
is represented by Vthp.
For the sense amplifier SA to start sensing operation at time T
02
, gate to source potentials Vgs of the sense transistors SAN
1
, SAN
2
, SAP
1
, and SAP
2
must be greater in absolute value than the threshold voltages Vthn and Vthp. When the very small potential difference dV between the bit lines BL and ZBL is disregarded, the following relationship is satisfied before the sensing operation:
Vgs=Vbl
=1/2×
Vdds.
When the following relationship holds, the sense amplifier SA securely starts sensing operation:
Vdds
>max{2
×Vthn,
2
×|Vthp|}.
When the following relationship holds, the sense amplifier SA does not start the sensing operation:
Vdds
<min{2
×Vthn,
2
×|Vthp|}.
In addition, one of the values of Vgs−Vthn and Vgs−|Vthp| significantly influences an initial speed of the sensing operation of the sense amplifier SA. When one of the values of Vgs−Vthn and Vgs−|Vthp| is reduced due to a reduction in
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