Semiconductor contact via structure and method

Details Semiconductor contact via structure and method Semiconductor contact via structure and method

1991-08-06

2002-09-24

Jackson, Jr., Jerome (Department: 1109)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S648000, C438S656000, C438S672000, C438S742000, C438S970000

Reexamination Certificate

active

06455412

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more specifically to a structure and method for use in fabricating contacts between levels of a semiconductor device.
2. Description of the Prior Art
In semiconductor devices, metal lines are used for transmitting signals and for connection to the power supply. When a contact must be made to a lower conducting layer through an insulating layer, a contact via, or opening, must be formed through the intervening insulating layer.
In order to compensate for mask misalignment and other process variations, narrow metal lines are made larger at the point where they pass over a contact via. This is done since metal from the signal line must completely fill the bottom of the via. If the via is not completely filled, later process steps will affect the quality of the contact.
A minimum enclosure defines the extra surface area which must be added to a signal line in order to compensate for process variations. The widened portion is typically approximately twice the signal line width for small geometry devices. For example, if a device has metal signal lines with a 0.8 micron width, the region over a contact might be 2.0 microns wide. This enlarged area can be centered on the metal signal line, or may be offset to one side, and compensates for mask misalignment.
FIG. 7
shows a plan view of a typical prior art structure for making a contact through a via. A metal signal line
10
is designed to make contact to an underlying conducting layer through a contact via
12
. A widened portion
14
of the signal line
10
is centered over the contact
12
. The minimum enclosure is the distance
16
between the edge of the widened portion
14
and the edge of the contact via
12
. Process variations may cause the actual alignment of the widened portion
14
to vary with respect to the contact via
12
.
It would be desirable to provide a process for fabricating semiconductor devices, and a structure formed thereby, which ensures adequate metal contact through a contact opening while reducing the minimum enclosure requirement.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a structure and method for fabricating contacts in semiconductor devices which allows minimum enclosure requirements to be reduced.
It is another object of the present invention to provide such a structure and method which provides high quality contacts.
It is a further object of the present invention to provide such a structure and method which minimizes added complexity to the process of fabricating contacts.
Therefore, according to the present invention, a contact opening through an insulating layer is filled with metal and etched back to form a metal plug within the opening. A metal interconnect line can then be formed over the contact, and makes electrical contact with the metal plug. Since the contact opening is filled by the metal plug, it is not necessary for the metal signal line to have a widened portion in order to ensure enclosure.


REFERENCES:
patent: 3499213 (1970-03-01), Domel et al.
patent: 4720908 (1988-01-01), Wills
patent: 5110762 (1992-05-01), Nakahara et al.
patent: 5141897 (1992-08-01), Manocha et al.
patent: 2206234 (1988-12-01), None
patent: 57-26431 (1982-02-01), None
patent: 64-48447 (1989-02-01), None
patent: 1-230253 (1989-09-01), None
Y. Panlean, “Interconnect Materials for VLSI circuits, Part II”, Solid State Technology, Apr. 1987 pp. 155-162.

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