Semiconductor with laterally non-uniform channel doping...

Details Semiconductor with laterally non-uniform channel doping... Semiconductor with laterally non-uniform channel doping...

2000-10-10

2002-04-30

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S306000, C438S525000, C257S339000

Reexamination Certificate

active

06380041

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to deep-submicron Metal-Oxide Semiconductors (MOS) and a manufacturing method therefor.
BACKGROUND ART
Deep-submicron Complementary Metal-Oxide-Semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) circuits. Scaling of CMOS has been the principal focus of the microelectronics industry over the last two decades.
As device sizes are scaled down, the source and drain junctions have to be scaled down. As the source and drain are scaled down, series resistance increases, which degrades the device performance. To reduce series resistance, advanced MOS transistors today have relatively deep source and drain junctions to improve series resistance and very shallow source and drain extension junctions to permit the scale down.
With the very shallow source and drain extension junctions which allow the source and drain to be closer together, the channel length between the source and drain is shortened. The shortening in the channel length has lead to several severe problems.
First, with high drive currents, the leakage across the channel is unacceptably high when the transistor is supposed to be off.
Second, the transistors have low manufacturability because of a high range in off current spread between nominal and sub-nominal devices.
Third, the so-called short channel effects (SCE), which degrade the performance of the scaled MOS devices, increase disproportionately with the shortened channel. Basically, the threshold voltage for turning the transistor on and off is nonlinearly lower for sub-0.18 micron transistors than it is for a 0.18 micron transistor and even worse for a sub-0.13 transistor, making it much, much harder to control the smaller transistors.
The conventional approach has been to provide deep sub-micron transistors with laterally uniform channel doping profiles which are scaled down from larger transistors. This approach does not solve the above problems.
Although it has long been known that laterally non-uniform channel doping profiles could be the solution to these problems and although there have been a number of attempts to provide laterally non-uniform channel profiles through direct doping, all of the previous attempts have been uniformly unsuccessful in solving all the problems.
DISCLOSURE OF THE INVENTION
The present invention provides a semiconductor having a laterally non-uniform channel doping profile with a peak beneath a comer of the gate.
The present invention provides a semiconductor having a laterally non-uniform channel doping profile by using a Group IV element implant to create interstitials under at least one bottom corner of the gate and channel doping followed by a rapid thermal anneal to drive the channel dopant into the channel making use of increased effects of transient enhanced diffusion (TED).
The present invention further provides a method of manufacturing a semiconductor having a laterally non-uniform channel doping profile by using angled implants to create interstitials under the gate and implant dopants under the gate followed by a rapid thermal anneal to drive in the channel doping.
An advantage of the present invention is that it stops current leakage across the channel when the transistor is off.
Another advantage of the present invention is to make a high-manufacturability transistor with a low off current spread between nominal and sub-nominal devices.
A further advantage of the present invention is to make a transistor where the turn on and turn off voltages are linear with shortening channel length, i.e., so there is a minimum amount of threshold voltage roll-off.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5409848 (1995-04-01), Han et al.
patent: 5510279 (1996-04-01), Chien et al.

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