Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-12
2002-09-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06449743
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to test sequence generation technique used in fault testing for an integrated circuit (LSI).
As one of conventional methods of generating test sequences, a method using a time expansion model has been proposed (“An RT Level Partial Scan Design Method Based on Combinational ATPG”, Inoue et al., TECHNICAL REPORT of IEICE, FTS96-67, February 1997, issued by Fault Tolerance Research Group of The Institute of Electronics, Information and Communication Engineers).
FIG. 48
is a flowchart for showing the outline of procedures in the method of generating test sequences using a time expansion model. As is shown in
FIG. 48
, an acyclic sequential circuit or an integrated circuit designed as a sequential circuit having an acyclic structure in testing is subjected to timeframe expansion, so as to generate a time expansion model (S
210
). Test patterns for detecting faults set with respect to the time expansion model are generated, so as to execute fault simulation (S
220
). Then, the test patterns generated with respect to the time expansion model are transformed into test sequences applicable to the original sequential circuit (S
230
).
In the conventional method of generating test sequences, the test patterns generated with respect to the time expansion model, that is, a combinational circuit, cannot be directly applied to the original sequential circuit as described above. Therefore, it is necessary to transform the test patterns into test sequences applicable to the original sequential circuit.
The transformation of test patterns into test sequences itself is comparatively easy. However, when test patterns are transformed into test sequences without giving any particular consideration, although the transformation process can be easily conducted, the ultimately obtained test sequences can be unnecessarily long as a whole. This can cause a serious problem in actual application of the method of generating test sequences using a time expansion model to design and fabrication of integrated circuits. However, no effective approach has been made to this problem.
SUMMARY OF THE INVENTION
An object of the invention is efficiently shortening test sequences obtained through test sequence generation using a time expansion model.
Specifically, the method of generating test sequences of this invention for use in fault testing for an integrated circuit comprises the steps of generating a time expansion model including a combinational circuit by subjecting the integrated circuit to timeframe expansion; and transforming test patterns generated with respect to the time expansion model into test sequences with respect to the integrated circuit, with compaction accompanied.
Preferably, the method of generating test sequences further comprises a step of generating a compaction template by compacting one or more primitive templates indicating whether or not a primary input or a pseudo primary input is present in each label of the time expansion model, and in the step of transforming test patterns, the test sequences are generated by substituting each of the test patterns in the compaction template and connecting resultant compaction templates.
In the method of generating test sequences, in the step of transforming test patterns, the compaction is preferably conducted in accordance with a compaction operation using three values of “don't care”, “0” and “1”.
In the method of generating test sequences, the step of transforming test patterns preferably includes substeps of subjecting an already generated test sequence to reverse transformation in process of test sequence transformation; executing fault simulation for the time expansion model by using a new test pattern obtained through the reverse transformation; and removing a fault detected in the fault simulation from a target of subsequent test sequence generation.
In the method of generating test sequences, the step of transforming test patterns preferably includes substeps of storing a generated test pattern in a test pattern compaction buffer, with compaction accompanied; when a test pattern is overflown from the test pattern compaction buffer, executing fault simulation for the time expansion model by using the overflown test pattern, so as to remove a fault detected in the fault simulation from a target of subsequent test sequence generation; transforming the overflown test pattern into a test sequence and compacting the resultant test sequence with an already generated test sequence; and subjecting the compacted test sequence to reverse transformation, so as to store a new test pattern obtained through the reverse transformation in the test pattern compaction buffer, with compaction accompanied.
Also, in the method of generating test sequences, the step of transforming test patterns preferably includes, in transforming one test pattern into a test sequence, substeps of executing fault simulation for the time expansion model by using the test pattern; obtaining a maximum value of labels including a primary output where a fault is detected in the fault simulation; and transforming the test pattern into a test sequence without using a value of a primary input belonging to a label with a value larger than the maximum value.
Alternatively, in the method of generating test sequences, the step of transforming test patterns preferably includes, in transforming one test pattern into a test sequence, substeps of executing fault simulation for the time expansion model by using the test pattern; specifying a primary input reachable from a primary output where a fault is detected in the fault simulation; and transforming the test pattern into a test sequence with a value of a primary input excluding the specified primary input set to “don't care”.
REFERENCES:
patent: 5502729 (1996-03-01), Nakata
Nierman et al. “Test Compaction for Sequential Circuits” Feb. 1992 IEEE Transactions on Computer-Aided Design pp. 260-267.*
T.M. Niermann et al., “Test Compaction for Sequential Circuits”, IEEE Transactions on Computer-Aided Design, vol. 11, No. 2, pp. 260-267, Feb. 1992.
T. Inouoe et al., “An RT Level Partial Scan Design Method Based on Combinational ATPG”, Technical Report of IEICE. FTS96-67, pp. 73-80, Feb. 1997.
De'cady Albert
Harris Cynthia
Nixon & Peabody LLP
Studebaker Donald R.
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